Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Video: DVCon 2011 Update From NextOp CEO Yunshan Zhu

At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where…

• less than a min read
Cadence Connections , NextOp , uvm , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Zhu , Palladium XP , SVA , DVcon , assertion synthesis , MDV , IEV , Formal verification , IFV , IES-XL

Verification

Save The Date: Free Webinar on Automated SoC Connectivity Verification This Thursday…

We interrupt our technically oriented blogging to shamelessly promote a free webinar…

• 1 min read
ABV , methodology , Functional Verification , formal , SoC Connectivity , IEV , Formal verification , IFV

Analog/Custom Design

Is China Ready for Next Generation Mixed-signal Design?

A Chinese design engineer told me that his manager once told him: "You do not have…

• 4 min read
China , mixed-signal ToT , tech on tour , abstraction , EDA360 , analog , Mixed-Signal , Convergence , intent , japan , Silicon Realization , mixed signal , SoCs

Analog/Custom Design

Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

As more and more custom/analog designs migrate to advanced process nodes (<65nm)…

• 4 min read
AMS , parasitic-aware design , PAD , RAP , Virtuoso IC6.1.5 , custom/analog , PCells , Advanced Node , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , rapid analog prototyping , Custom IC Design , modgens , Virtuoso Layout Suite , parasitics

Analog/Custom Design

Early Analysis is Key – Parasitic-Aware Design

Decreasing geometries and increasing design complexity are making the task of designing…

• 3 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , IC 6.1.5 , ADE , Virtuoso , ADE-GXL , ADE-XL , parasitics

System, PCB, & Package Design 

What's Good About Capture OLE Object Placing? You Can Easily Do This in SPB16.3!

Object Linking and Embedding ( OLE ) support in SPB16.3 Allegro Design Entry CIS…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Design Entry CIS , OrCAD Capture , SPB 16.3 , Capture CIS , Capture-CIS , OLE , SPB , design , OrCAD , object placing , Design Entry , PCB Capture

Digital Design

28 nm IC Design: The Devil Is In The Details

Smaller process technologies are enticing chip makers with bigger rewards from their…

• 4 min read
EDI , lithography , CMP , Litho , 28nm , DRC , metal thickness , LVS , Advanced Node , NanoRoute , encounter , via rules , LPE , digital , Silicon Realization , Digital Implementation , interconnect rules , Variation , stress , parasitics

Analog/Custom Design

Virtuoso IC6.1.5: Software and Fine Red Wine

Software, like fine red wine, can get better with age as well -- but it requires…

• 7 min read
AMS , parasitic-aware design , Low Power , Virtuoso IC6.1.5 , custom/analog , Analog Simulation , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , mixed signal , Custom IC Design , DFM , parasitics

Verification

A Modest Proposal: Using Formal to Close Coverage Gaps

In my last blog post , I summarized some of our activities at DVCon and mentioned…

• 4 min read
NextOp , coverage , Functional Verification , Formal Analysis , formal , BugScope , Breker , DVcon , assertion synthesis , assertions , Closure , metrics , CVC , Formal verification

Verification

DATE Spotlights System Development University Investment in Europe

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's…

• 2 min read
university , DATE , Winterholer , UML , Daedalus , University Booth , VOCIS , System Design and Verification

RF Engineering

Tips for Simulating a Transmit Mixer in SpectreRF

Some typical questions that I receive from newer SpectreRF users are: How do I simulate…

• 8 min read
RF , RF Simulation , Spectre RF , ADE-L , Analog Simulation , MMSIM , spectreRF , Spectre , RF design , harmonic balance , mixer

Digital Design

Encounter Puzzler #3 Solution: Renaming a Net Logically

Once again, the Encounter Digital Implementation designer community has stepped up…

• 4 min read
conformal , dbGet , net renaming , encounter , Digital Implementation , Encounter Digital Implementation , puzzler , tcl

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? Check Out the ADW16.3 Release and See!

The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers…

• 4 min read
PCB , SPB16.3 , Allegro Design Entry , part developer , DEHDL , mechanical parts , Directive Lockhing , Allegro 16.3 , SPB 16.3 , High Speed , Allegro Design Workbench , Library flow , SPB , LRM , PCB Editor , Design Entry HDL , design data management , design , Library Revision Manager , "PCB design" , PCB design , Design Entry , ADW 16.3 , Allegro PCB Editor , Librarians , ConceptHDL , library , ADW , Schematic

Verification

Video: Optimizing Area and Power Using Formal Methods

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel…

• 1 min read
Low Power , ABV , methodology , Formal Analysis , formal , Freescale , Incisive , Chris Komar , DVcon , IFV

Verification

Video: New Cadence Verification IP Catalog (With Denali Inside!)

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news…

• less than a min read
uvm , Functional Verification , ABVIP , Cadence VIP portfolio , OVM , VIP , EDA360 , Verification IP modeling , DVcon , eRM

Verification

TLM 2.0, UVM 1.0 and Functional Verification

The DVCon 2011 conference was held this week and the Accellera Universal Verification…

• 8 min read
SystemVerilog , uvm , TLM , Functional Verification , OVM , TLM 2.0 , ports , DVcon , Accellera , SystemC , Accellera VIP TSC , VMM , verification

Verification

DVCon? Are You Sure It's Not UVMCon or MSVCon?

As I write this, I've just returned from the most important conference and tradeshow…

• 2 min read
uvm , Functional Verification , MSV , EDA360 , Mixed-Signal , random test , DVcon , Accellera , mixed signal , verification

System, PCB, & Package Design 

What's Good About Cadence Online Support Product Pages? – Check Out This List!

I wrote about the new Cadence Online Support features in one of my blog posts last…

• 2 min read
PCB SI , PCB , SCM , PCB Layout and routing , SI , SPB16.3 , Allegro Design Entry , AMS , SiP , PCB PI , IC Packaging , Design Entry CIS , social networking , Signal Intregrity , DEHDL , FPGA-PCB Co-Design , Digital SiP design , specctra , SigXP UI , FPGA System Planner , OrCAD Capture , Allegro 16.3 , Capture CIS , Capture-CIS , High Speed , APD , Support , Smoke Analysis , SigWave , SPB , webinar , SPB16.2 , PCB Editor , Constraint Manager , Design Entry HDL , ASA , Layout , design , FSP , OrCAD , PCB Signal integrity , PCB design , Design Entry , windows 7 , Allegro PCB Editor , Librarians , SI analysis and modeling , ConceptHDL , SPB16.01 , OrCAD PCB Editor , GRE , Online Support , library , ADW , PCB Capture , Schematic , FPGA , Allegro

Verification

Specman Application Note: Improving Verification Productivity With Dynamic Load and…

Are you looking for new approaches to improve your verification productivity by 40…

• 3 min read
IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , vPlan , simvision , EDA , Incisive , e language , team specman , specman elite , Aspect Oriented Programming , testbench , Incisive Enterprise Simulator (IES) , AOP , IES-XL
CDNS - Fix Layout Hompage