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Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
Corporate 30 Jun 2026 • 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

  • All 6438
  • Corporate News 266
  • Life at Cadence 206
  • Academic Network 169
  • Analog/Custom Design 804
  • Artificial Intelligence 28
  • Cloud 24
  • Computational Fluid Dynamics 375
  • Data Center 60
  • Digital Design 465
  • Learning and Support 63
  • RF Engineering 116
  • SoC and IP 435
  • System, PCB, & Package Design  1017
  • Verification 1332
  • Cadence Japan 18
  • Physical Systems Simulation 25

  • CFD(数値流体力学) 45
  • 中文技术专区 9
  • カスタムIC/ミックスシグナル 199
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 45
  • Spotlight Taiwan 64
  • The India Circuit 93
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Vision C5 DSP: A Solution to Current Challenges and Trends…

In this week's Whiteboard Wednesdays video, Megha Daga talks about how Cadence did…

References4U 30 May 2017 • less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Virtuoso System Design Platform

Cadence was already talking about chip-package-board back in 2000 when I was putting…

Paul McLellan 30 May 2017 • 3 min read
package , board , 2.5D packagin , Virtuoso , 3D packaging , interposer , Sigrity , Custom IC , Breakfast Bytes , Allegro

Academic Network

10 years Academic Network at CDNLive EMEA, a Reason To Celebrate!

From 15-17 May CDNLive EMEA opened again its doors for around 700 attendees from…

Anton Klotz 26 May 2017 • 5 min read
Cadence Academic Network , CDNLive , BarCamp , Functional Verification , academic workshop , academia , MEMS Design Contest , CDNLive EMEA , Cadence Design Contest , university program

Analog/Custom Design

Virtuoso Video Diary - Filtering Your Way Through Corners

Have you ever looked at the Corners Setup form and wished you had some way of finding…

Arja H 26 May 2017 • 4 min read
Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso , Analog Design Environment , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Assembler

Breakfast Bytes

HOT Party Remembers Gary Smith...and the Denali Party

Every year at DAC, Heart of Technology (HOT) organizes a charity event. This year…

Paul McLellan 26 May 2017 • 2 min read
DAC , HOT , Heart of Technology , Gary Smith , sjsu , Design Automation Conference , Breakfast Bytes

System, PCB, & Package Design 

Epic Western Movies and PCB Design. Seriously.

I love that recently Westerns movies are making a comeback. Something about the romanticism…

Darintb 25 May 2017 • 2 min read
PCB , PCB Layout and routing , Routing , PCB Co-Design , Symphony , Team design , PCB Editor , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

Open-Source Silicon

At the RISC-V workshop in Shanghai, the keynote on the second day was by Bunnie Huang…

Paul McLellan 25 May 2017 • 12 min read
security , open source silicon , root of trust , bunnie huang , open source hardware , open source , Breakfast Bytes

Verification

Have You Fully Verified Your Multi-Core, Cache-Coherent SoC? Find Out How we Can…

You might have thought it would be “just another DAC” this year, again in Austin…

Steve Brown 24 May 2017 • 3 min read
DAC , SoC verification , Perspec , pss , Accellera PSS

Breakfast Bytes

What's For Breakfast? Video Preview May 29th to June 2nd 2017

https://youtu.be/xTdQCRRme8U Coming from Mexico City, Mexico (camera Yuan Yuan…

Paul McLellan 24 May 2017 • less than a min read
hololens , microsoft , deep learning , embedded vision , Tensilica , Virtuoso

System, PCB, & Package Design 

How Your PCB Design Team Can Become Your Dream Team for Power Integrity

Cadence’s Sigrity team speaks to a lot of power integrity tool users. Experts in…

Sigrity 24 May 2017 • 3 min read
PCB , PI , PDN , Power Integrity , Layout , Sigrity , simulation , Schematic

Breakfast Bytes

RISC-V Shanghai 二

This is my second (二 in Chinese) post about the 6th RISC-V workshop held in early…

Paul McLellan 24 May 2017 • 8 min read
computer architecture , risc-v , isa , instruction set architectures , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Convolutional Neural Network Challenges: Bandwidth Requi…

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into bandwidth…

References4U 23 May 2017 • less than a min read
Whiteboard Wednesdays , convolutional neural networks , bandwidth

Breakfast Bytes

Fifty Years of Computer Architecture: The Last 30 Years

As part of the RISC-V workshop, Dave Patterson gave a talk on computer architecture…

Paul McLellan 23 May 2017 • 6 min read
risc-v , CISC , AMD , titanium , vliw , RISC , Breakfast Bytes

Breakfast Bytes

Fifty Years of Computer Architecture: The First 20 Years

As part of the RISC-V workshop, Dave Patterson gave a talk on computer architecture…

Paul McLellan 22 May 2017 • 6 min read
Intel , risc-v , CISC , RISC , ibm 360 , Breakfast Bytes , dave patterson

Breakfast Bytes

Dream Chip: A Vision for Your Car

Dream Chip is a company based in Germany just outside Hannover. Martin Zeller presented…

Paul McLellan 19 May 2017 • 4 min read
Automotive , dreamchip , 22fdx , ADAS , GlobalFoundries , Breakfast Bytes , FD-SOI

Analog/Custom Design

Virtuosity: Is it Possible to Create a Bus on Several Metal Layers Simultaneously…

Routing Multiple Nets on Different Metal Layers to Gain Productivity Have you…

Parula 19 May 2017 • 7 min read
transitioning capabilities , space-based router , weAddCustomTransitionMenuItem , customizing multi-layer bus , weRemoveCustomTransitionMenuItem , custom layer pattern , switching bus bits , weGetCustomTransitionMenuItems , multi-layer bus , stacked wires , Layout , Virtuosity , revert to multi-layer bus

Breakfast Bytes

CDNLive EMEA Zwei

This is the second post about CDNLive EMEA in Munich. Here is the first . If the…

Paul McLellan 18 May 2017 • 9 min read
CDNLive , virtual platform , CDNLive EMEA , Bosch , CDNLive Munich , OrCAD , ARM , arrow , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 22nd to 26th 2017

https://youtu.be/Frsw0YkUF5M Coming from Marienplatz, Munich, Germany (camera…

Paul McLellan 17 May 2017 • less than a min read
open source silicon , computer architecture , risc-v , Heart of Technology , Denali Party , isa , Denali , open source , instruction set architecture

Whiteboard Wednesdays

Whiteboard Wednesdays – Tensilica Fusion G6 DSP Takes on Automotive ADAS Radar A…

In this week's Whiteboard Wednesdays video, Pushkar Patwardhan gives an overview…

References4U 17 May 2017 • less than a min read
DSP , Whiteboard Wednesdays , fusion G6 , Fusion G3 , radar , Tensilica , Fusion DSP Family
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