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Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

Hamid Shojaei
• 14 min read
featured , AI in chip design , GenAI , AI/ML
cdns - all_blogs_categories

Blog - Post List
Latest blogs

RF Engineering

Setting VIVA Waveform Color Defaults When Using ADE

I found myself getting a little bit frustrated with some of the default colors that…

• less than a min read
MMSIM71 , Virtuoso Spectre , spectreRF , Spectre , RF design

Analog/Custom Design

OpenAccess, Its Just a Database…

I suspect that in another year we’ll all stop talking about OpenAccess (OA) like…

• 3 min read
ecosystem , Virtuoso Analog Design Environment , Virtuoso , PDK , Custom IC Design , Process Design Kit , custom design technology

Verification

CtoS support of Multiple Clocks

In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support…

• less than a min read
High-Level Synthesis , CTOS , clock , System Design & Verification , SystemC , C-to-Silicon Compiler , clocking

Verification

Totally Off Topic: It's A Girl!

Allow me to digress from EDA subjects to herald the birth of my first child! …

• less than a min read
baby , Functional Verification , team specman , girl

Verification

Embedded Software on the Virtual Platform: Analog or Digital?

One of the things I learned when Verisity purchased Axis was the difference in mindset…

• 4 min read
Specman , virtual platform , System Design and Verification , analog , Enterprise Manager , waveform , functional coverage , ISX , check pointing , Jason Andrews

Verification

The Cadence ESL Machine Keeps Building Momentum!

Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon…

• 3 min read
System Design and Verification , Palladium , EDN , C-to-Silicon , EDN Innovation award

Verification

Performance-Aware e Coding Guidelines – Part 4

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve…

• less than a min read
IEEE 1647 , performance , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , OVM-e , specman elite , sequences , IES , IES-XL

System, PCB, & Package Design 

What's Good About TCL, P&S, STUFF in ASA? The Secret's in the SPB16.2 Release!

OK - so maybe I got a little bit too happy with acronyms (STUFF doesn't represent…

• 3 min read
ActiveTcl , SCM , SPB 16.2 , ASA , PCB design , Allegro , tcl

Verification

C-to-Silicon Support of Concurrent Processes

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to C …

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , SystemC , ESL

Analog/Custom Design

Part 1 - Constraint-driven Physical Design Speeds Custom IC Design Convergence

In this introductory Part I of V of this blog I will discuss the advanced node design…

• 1 min read
Virtuoso Space-based Router , VSR , IC 6.1 , CMP , chip optimizer , Litho , DFY , CAA , Constraint-driven , Virtuoso IC 6.1.3 , Connectivity-driven , IC 6.1.4 , Custom IC Design , space based router , DFM

Verification

Industry Discussion about High Level Synthesis

Many of you know that Richard Goering has joined Cadence and now writes a blog called…

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , Richard Goering , incisive c-to-silicon

Verification

Survey Results For "Booth-Centric" vs. "Paper Centric" Shows

In my last post I shared how my annual tour of the tour of the ESC show floor inspired…

• 2 min read
events , DAC , Specman , CDNLive , Functional Verification , CDNLive San Jose 2008 , ESC , DVcon , Xuropa

Digital Design

Noise Induced Double Clocking Explained

In my previous blog on noise analysis accuracy , I mentioned something called “double…

• 1 min read
CadMOS , encounter , Digital Implementation , double clocking , Enouter Timing System , CeltIC

Analog/Custom Design

IC Design vs. Manufacturing Objectives - Can Both Be Achieved Concurrently?

IC designers and foundries typically have different objectives. IC designers want…

• 3 min read
Chip finishing , Virtuoso Space-based Router , Physical placement and layout , Virtuoso IC 6.1.3 , IC 6.1.4 , Custom IC Design , custom design technology

Verification

Performance-Aware e Coding Guidelines – Part 3

The constraint solver is a powerful and fun to use tool. Actually, it is so much…

• 1 min read
performance , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES , IES-XL

Digital Design

Constraint Construction: What's Its Function? Part 4 of 4

This is the last in the series of Constraint Construction blogs ! Today we're going…

• 2 min read
design rules , encounter , rtl compiler , Digital Implementation , modes of operation

System, PCB, & Package Design 

What's Good About DEHDL-CM Physical and Spacing Constraints? You'll need SPB16.2

That's right - the SPB16.2 release now includes support for Physical and Spacing…

• 2 min read
16.01 , SPB 16.2 , DEHDL , Design Entry HDL , PCB design , Allegro

Verification

Homeschoolers Hungry for Technology

Over the weekend I attended the 2009 Minnesota Homeschool Conference in downtown…

• 4 min read
System Design and Verification , Lego , mindstorms NXT

Digital Design

Encounter Digital Implementation System 8.1 San Jose Live Blog

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar…

• less than a min read
Low Power , encounter , Digital Implementation , mixed signal , design closure , Encounter Digital Implementation System 8.1
CDNS - Fix Layout Hompage