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Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

Hamid Shojaei
• 14 min read
featured , AI in chip design , GenAI , AI/ML
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

New Technical Blog on e & Specman Technology

Specmaniacs of the world: rejoice! Members of Team Specman have just launched their…

• less than a min read
IEEE 1647 , Specman , e

Verification

Constraint layering - Fine Tuning Your Environment - Part 1

In today's environment of ever growing complexity and ever shrinking schedules,…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , verification strategy , Verification methodology , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Verification

New e / Specman Workshops Available Now

In response to the continual growth in the e /Specman user community, Team Specman…

• 2 min read
workshops , IEEE 1647 , Specman , metric driven verification (MDV) , Functional Verification , Testbench simulation , MDV techtorial , OVM e , Coverage-Driven Verification , e , Kit , coverage driven verification (CDV) , eRM , IES

Verification

New Blog - All About e & Specman

End-users of e , Specman, Incisive Enterprise Simulator (IES), e RM/OVM e , and…

• 1 min read
IEEE 1647 , Specman , verification strategy , metric driven verification (MDV) , Functional Verification , Testbench simulation , OVM e , Coverage-Driven Verification , e , coverage driven verification (CDV) , eRM , Incisive Enterprise Simulator (IES) , IES

System, PCB, & Package Design 

What's Good About SPB16.2 OrCAD Capture? Many Usability Enhancements!

There are enormous usability updates in the SPB16.2 release of OrCAD Capture. From…

• 7 min read
SPB 16.2 , OrCAD , PCB design

Analog/Custom Design

What's New With Virtuoso?

If you were wondering what's new with Virtuoso you may want to check out the latest…

• less than a min read
MMSIM , Floorplanning , Virtuoso IC 6.1.3 , Virtuoso , RF design , Custom IC Design

Verification

Metric Driven System Level Verification

I have the great honor of introducing a wonderful paper on system level verification…

• 1 min read
System Design and Verification , ARC International , ISX

Verification

VMM Users -- Welcome to the OVM!

VMM users -- welcome to the OVM! We've been talking together about the benefits…

• 3 min read
SystemVerilog , Verification methodology , Functional Verification , OVM , VIP , e , eRM , OVMWorld

Digital Design

3 Reasons Why You Will Want to Download Encounter 8.1

Today is a big day in Digital Implementation land here at Cadence. Looking around…

• less than a min read
Flows , SoC-Encounter 8.1 , Low-Power , Digital Implementation , Floorplanning and Prototyping

System, PCB, & Package Design 

What's Good About the SPB16.2 Cross Referencer? Active Links in the Schematic!

That's right - an often requested feature from several customers has now been implemented…

• 2 min read
SPB 16.2 , PCB design

Digital Design

Innovate Your Way Out of Recession With the New Encounter!

It's official! The U.S. economy has been in a recession for the past year. …

• 2 min read
Static timing analysis , Early Rail Analysis , SoC-Encounter , Digital Implementation forums , First Encounter , SoC-Encounter 8.1 , Signoff Analysis , STA , encounter , Cadence Encounter Power System , Digital Implementation , CeltIC NDC , Global Timing Debug , Encounter Timing System , SSTA , Floorplanning and Prototyping , "SoC-Encounter"

Verification

News From the IP '08 Conference

My colleagues on the Verification IP team have been honored to present at the annual…

• 3 min read
HW/SW , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , VIP , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , Verification IP modeling , ISX

Digital Design

Demo: Using the Pin Editor in SoC-Encounter

SoC-Encounter has automatic partition pin assignment capabilites. The tool also…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , Digital Implementation , Pin Editor

Verification

Follow-up on Posedge Software Interview

Just a quick follow-up to my previous interview with Henry Von Bank of Posedge Software…

• less than a min read
posedge , System Design and Verification , ISX

Verification

e Running Inside VCS Anniversary Updates?

It's been a year since I heard the first solid report about Synopsys supporting…

• less than a min read
IEEE 1647 , Specman , Testbench simulation , e , multi-language , Incisive Enterprise Simulator (IES) , IES

Digital Design

Tapeout!

With an early December tapeout looming, I've found myself too busy to write a post…

• 3 min read
ECO , LEC , DRC , LVS , Digital Implementation , Power Analysis , tapeout

System, PCB, & Package Design 

What's Good About Advanced Plating Bar Checks - Check out the SPB16.2 Release and…

New functionality has been added to the SPB16.2 Allegro Advanced Package Designer…

• 7 min read
SPB 16.2 , BGA , advanced package designer , advanced plating bar check , PCB design , Allegro

Verification

Virtualization and Verification With Posedge Software

Posedge Software is a Cadence Verification Alliance Member with skills in two of…

• 5 min read
posedge , open virtual platforms , System Design and Verification , OVP , QEMU

Verification

Thoughts on AMS Verification Inspired by the DV Club Lunch

Last week I had the pleasure of attending a DV Club lunch presentation from Dr.…

• 2 min read
AMS , verification strategy , Verification methodology , Functional Verification
CDNS - Fix Layout Hompage