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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Digital Design

Get on Board With Bus Guides

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you…

• 2 min read
Bus Guides , encounter , 8.1 , Digital Implementation

System, PCB, & Package Design 

What's Good About Cline Change Width in APD? It's in SPB16.2!

In IC package design, it is becoming increasingly necessary to change a cline’s width…

• 2 min read
SPB 16.2 , APD , PCB design , Cline change

Verification

Generation Action: Constraints From Above

[Welcome guest blogger Reuven Naveh of Specman R&D] What is the “constraints from…

• 6 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Verification

Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty…

• 1 min read
System Design and Verification , Palladium , incyte , C-to-Silicon Compiler

Analog/Custom Design

Moving an Ecosystem

Recently, a colleague here at Cadence created the image of an ecosystem , whose existence…

• 1 min read
ecosystem , Virtuoso , CAD , Custom IC Design

SoC and IP

Company Financials for 4Q08. Not Good

Memory Makers lose $8.8B in 4Q2008, to bring annual losses to $20B: Memory companies…

• 14 min read

Verification

Tracing TLM 2.0 Activity In An ESL Design – Part I

Many design teams that use SystemC are in various stages of evaluating TLM 2.0 –…

• 6 min read
TLM , System Design and Verification , TLM 2.0 , SystemC analysis , George Frazier , sctlmrecord , ESL

Verification

Making the Right Decisions *Before* You Start Your Project

Seems logical, but unfortunately, I run into customers today that grumble about their…

• 3 min read
InCyte IP , chipestimate , System Design and Verification , chip estimation

Verification

Connecting OVM Testbench and SystemC TLM2 IP

1. Introduction With TLM2 enabling more sophisticated SystemC IP interoperability…

• 9 min read
TLM2 IP , System Design and Verification , OVM , SystemC , testbench

Verification

C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other…

• 1 min read
ECO , CTOS , RTL , System Design and Verification , C-to-Silicon , ESL

Verification

IMPORT Guidelines For e, Part 1

[Team Specman welcomes AE Manager Avi Behar as our newest guest blogger] Hi, my name…

• 4 min read
IntelliGen , Specman , Functional Verification , Avi Behar , OVM e , Register Package , e , OVM-e , specman elite , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Digital Design

'Back to School' in April? Are you Kidding?

No, I am not kidding. in fact, we have planned several 'back to school' seminars…

• 1 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Manufacturability sign-off , 8.1 , Digital Implementation , "SoC-Encounter" , Encounter Digital Implementation System 8.1

Verification

DVCon '09 SaaS Panel Thoughts, Part 2

In my last post on the DVCon 2009 panel on Software As A Service , or " SaaS " as…

• 3 min read
security , SaaS , Functional Verification , Harry The ASIC Guy , DVcon

RF Engineering

Setting Up Harmonic Balance - Part 1

This is the first of a series of Blogs to talk about how to fill out the forms for…

• 3 min read
MMSIM71 , Spectre RF , spectreRF , RF design , harmonic balance

System, PCB, & Package Design 

What's Good About Dynamic Fillets in Allegro PCB Editor? Check out the SPB16.2 Release

The existing Fillet application, a function of the Gloss routine, has been enhanced…

• 1 min read
SPB 16.2 , PCB Editor , Allegroro , PCB design , Dynamic Fillets , t-juntions

System, PCB, & Package Design 

It’s All In The Metrics

You could be forgiven for thinking that this was going to be a discussion of the…

• 3 min read
Allegro Design Workbench , PCB design , metrics , enterprise integration

Digital Design

Does Noise Analysis Accuracy Really Matter?

There have been a lot of new faces springing up in the signoff analysis market over…

• 2 min read
Static timing analysis , Signoff Analysis , STA , Advanced Node , Mixed-Signal , 8.1 , Encounter Digital Implementation , CeltIC NDC , Global Timing Debug , SSTA , "SoC-Encounter"

SoC and IP

Taiwan Memory Company (TMC), Part III

"EDIT: I have corrected Etron's 2007 P& L entry to show a net profit of 39M instead…

• 7 min read

Verification

New eDocs Makes Documenting Fun!

Documentation. This single word tends to sends shivers up the spine of many an engineer…

• 3 min read
Specman , Functional Verification , e , specman elite , OOP , hvl , AOP , verification
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