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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Totally Off Topic: It's A Girl!

Allow me to digress from EDA subjects to herald the birth of my first child! …

• less than a min read
baby , Functional Verification , team specman , girl

Verification

Embedded Software on the Virtual Platform: Analog or Digital?

One of the things I learned when Verisity purchased Axis was the difference in mindset…

• 4 min read
Specman , virtual platform , System Design and Verification , analog , Enterprise Manager , waveform , functional coverage , ISX , check pointing , Jason Andrews

Verification

The Cadence ESL Machine Keeps Building Momentum!

Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon…

• 3 min read
System Design and Verification , Palladium , EDN , C-to-Silicon , EDN Innovation award

Verification

Performance-Aware e Coding Guidelines – Part 4

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve…

• less than a min read
IEEE 1647 , performance , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , OVM-e , specman elite , sequences , IES , IES-XL

System, PCB, & Package Design 

What's Good About TCL, P&S, STUFF in ASA? The Secret's in the SPB16.2 Release!

OK - so maybe I got a little bit too happy with acronyms (STUFF doesn't represent…

• 3 min read
ActiveTcl , SCM , SPB 16.2 , ASA , PCB design , Allegro , tcl

Verification

C-to-Silicon Support of Concurrent Processes

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to C …

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , SystemC , ESL

Analog/Custom Design

Part 1 - Constraint-driven Physical Design Speeds Custom IC Design Convergence

In this introductory Part I of V of this blog I will discuss the advanced node design…

• 1 min read
Virtuoso Space-based Router , VSR , IC 6.1 , CMP , chip optimizer , Litho , DFY , CAA , Constraint-driven , Virtuoso IC 6.1.3 , Connectivity-driven , IC 6.1.4 , Custom IC Design , space based router , DFM

Verification

Industry Discussion about High Level Synthesis

Many of you know that Richard Goering has joined Cadence and now writes a blog called…

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , Richard Goering , incisive c-to-silicon

Verification

Survey Results For "Booth-Centric" vs. "Paper Centric" Shows

In my last post I shared how my annual tour of the tour of the ESC show floor inspired…

• 2 min read
events , DAC , Specman , CDNLive , Functional Verification , CDNLive San Jose 2008 , ESC , DVcon , Xuropa

Digital Design

Noise Induced Double Clocking Explained

In my previous blog on noise analysis accuracy , I mentioned something called “double…

• 1 min read
CadMOS , encounter , Digital Implementation , double clocking , Enouter Timing System , CeltIC

Analog/Custom Design

IC Design vs. Manufacturing Objectives - Can Both Be Achieved Concurrently?

IC designers and foundries typically have different objectives. IC designers want…

• 3 min read
Chip finishing , Virtuoso Space-based Router , Physical placement and layout , Virtuoso IC 6.1.3 , IC 6.1.4 , Custom IC Design , custom design technology

Verification

Performance-Aware e Coding Guidelines – Part 3

The constraint solver is a powerful and fun to use tool. Actually, it is so much…

• 1 min read
performance , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES , IES-XL

Digital Design

Constraint Construction: What's Its Function? Part 4 of 4

This is the last in the series of Constraint Construction blogs ! Today we're going…

• 2 min read
design rules , encounter , rtl compiler , Digital Implementation , modes of operation

System, PCB, & Package Design 

What's Good About DEHDL-CM Physical and Spacing Constraints? You'll need SPB16.2

That's right - the SPB16.2 release now includes support for Physical and Spacing…

• 2 min read
16.01 , SPB 16.2 , DEHDL , Design Entry HDL , PCB design , Allegro

Verification

Homeschoolers Hungry for Technology

Over the weekend I attended the 2009 Minnesota Homeschool Conference in downtown…

• 4 min read
System Design and Verification , Lego , mindstorms NXT

Digital Design

Encounter Digital Implementation System 8.1 San Jose Live Blog

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar…

• less than a min read
Low Power , encounter , Digital Implementation , mixed signal , design closure , Encounter Digital Implementation System 8.1

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 2

In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in…

• 4 min read
System Design and Verification , TLM 2.0 , George Frazier , SystemC , TLM 2.0 Trace

Verification

Another New Blog About the e Language

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Verification of AUTOSAR Software Using a SystemC Virtual Platform

[Please welcome ISX R&D team member Markus Winterholer back to the Team ESL blog…

• 2 min read
AUTOSAR , BSW , System Design and Verification , RTE , SystemC , VFB , ISX
CDNS - Fix Layout Hompage