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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About PCB SI AutoSolving Models in SigXplorer? You’ll Need the 16.6 Release…

In previous releases, when you extract a net into SigXplorer, all the structures…

• 2 min read
PCB SI , PCB , SI , Allegro GUI , Allegro 16.6 , IBIS , SigXP UI , 16.6 , "PCB SI" , High Speed , SigWave , SPB , Signal Integrity , design , "PCB design" , Allegro PCB SI , Grzenia , SI analysis and modeling , Allegro

Verification

DAC 2013 – Software Driven EDA for the “Age of Gods”

This year's Design Automation Conference is less than a week away, and it's time…

• 13 min read
virtual prototyping , DAC , virtual platforms , Acceleration , Cadence Theater , rapid prototyping , RTL simulation , software-driven EDA , System Development Suite , DAC 2013 , System-Level Design , Emulation , hybrid engines , Design Automation Conference , ESL , FPGA-based prototyping

Verification

Why are Cadence and Forte Presenting Together at DAC?

You may or may not have noticed that Cadence's DAC Theater schedule features an intriguing…

• 1 min read
High-Level Synthesis , DAC , C-to-Silcon Compiler , Forte Cynthesizer , SystemC , HLS

Verification

New Specman Coverage Engine - Extensions Under Subtypes

This is first in a series of three blog posts that are going to present some powerful…

• 4 min read
AF , Specman , Specman coverage engine , coverage , Functional Verification , when extensions , Incisive , e language , extensions under subtypes , metric-driven verification , coverage driven verification (CDV) , multi-instance coverage , verification coverage

RF Engineering

SpectreRF at 2013 IEEE/MTT-S International Microwave Symposium in Seattle, Washi…

If you are attending the International Microwave Symposium ( IMS 2013 ) in Seattle…

• less than a min read
nport , RF , RF Simulation , analog/RF , Circuit simulation , RFIC , Wilsey , shooting newton , Virtuoso Spectre , HB , Spectre RF , ADE-L , Analog Simulation , nport settings , MMSIM 12.1 , RF spectre spectreRF , spectreRF , RF design , International Microwave Symposium , harmonic balance

Analog/Custom Design

SKILL for the Skilled: Part 9, Many Ways to Sum a List

In the previous postings of SKILL for the Skilled , we've looked at different ways…

• 9 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early Adopter…

With every new release of the Cadence IC Package design software, many new features…

• 3 min read
SiP , IC Package , IC Packaging , feedback , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , beta tools , Allegro Package Designer , IC packaging documentation , early adopter , APD 16.6 , beta releases , wirebonding , IC Package Physical layout and co-design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!

Just a very "quick read" on a new option for Quickplace this week. The Allegro PCB…

• less than a min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Overlap components by , Placement Edit , place replicate , SPB , PCB Editor , Layout , Quickplace , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis…

The electronics industry has enjoyed constant growth while undergoing constant transformation…

• 3 min read
High-Level Synthesis , DAC , ASIC , microcontrollers , microprocessors , TLM , processors , TLM 2.0 , C , the internet of things , programmable world , Internet , SystemC , C-to-Silicon Compiler , HLS , microcontroller , C++

Analog/Custom Design

Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support

I'll confess: I didn't learn all of this strictly by browsing https://support.cadence…

• 2 min read
AMS , custom/analog , layout-dependent effects , Rapid Adoption Kit , 20nm , Virtuoso , Virtuosity , mixed signal , Custom IC Design

System, PCB, & Package Design 

What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now…

• less than a min read
Cadence Design Systems , AMS , cadence , AMS simulator , OrCAD Capture , Allegro AMS , PSPICE , design , OrCAD , AMS simulation , Grzenia

Analog/Custom Design

Things You Didn't Know About Virtuoso: Delta Markers in ViVA

This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while…

• 3 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC615 , IC 6.1.5 , delta markers , Analog Design Environment , ViVA , Custom IC Design

Verification

Mode Support for SimVision “Stop Simulation” Button

Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation…

• 1 min read
AF , Specman , debug , Functional Verification , stop simulation , simvision , Incisive , e language , stop Specman , IES

System, PCB, & Package Design 

What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!

Just a quick blog this week to mention a couple productivity enahancements for Capture…

• 1 min read
capture , Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , Design Entry CIS , Capture CIS , Capture-CIS , SPB , Front-end PCB design , design , Design Entry , Grzenia , Allegro

System, PCB, & Package Design 

Turn GDSII Data into Intelligent Die Components with 16.6 Cadence APD/SiP Tools

As we all know, there are many file formats in which an IC package designer will…

• 3 min read
Cadence Design Systems , SiP , IC Package , IC Packaging , GDSII , packaging , Digital SiP design , Advanced Package Router , stream , 16.6 , GDS-II , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , SiP Layout

System, PCB, & Package Design 

Customer Support Recommended - Instance and Occurrence Modes of Design Annotation…

Assigning reference designators for the schematic instances is a very vital part…

• 5 min read
PCB , 16.01 , capture , "capture CIS" , hierarchy , cadence , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , hierarchical schematics , Appnotes , Appnote , "PCB design" , OrCAD , PCB design , 16.5 , application note , PCB Capture , Schematic

Verification

Creating Virtual Platform Models

One of the most common questions asked about virtual platforms is:Who creates the…

• 4 min read
VSP Log Viewer , virtual prototoypes , virtual platforms , TLM , virtual platform models , cadence , TLM-2 , System Design and Verification , TLM 2.0 , SystemC modeling , TLM-2.0 , timgen , SystemC , Model creation , Cadence Virtual System Platform

System, PCB, & Package Design 

What's Good About ADW’s Design Migration? 16.6 has many new enhancements!

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required…

• less than a min read
Allegro 16.6 , cadence , 16.6 , Allegro Design Workbench , design data management , design , Grzenia , library , ADW , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 8, Many Ways to Sum a List (Closures -- Functions with…

In the past several postings to this blog, we've looked at various ways to sum a…

• 8 min read
Team SKILL , lexical closures , programming , Jim Newton , closures , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL
CDNS - Fix Layout Hompage