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Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design
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Blog - Post List
Latest blogs

Verification

A SystemC Virtual Platform Overflowing the Stack -- Just Before DAC

Thanks to all who stopped by the Cadence booth to see and talk about the Cadence…

• 6 min read
DAC , Virtual System Platform , virtual platforms , virtual prototypes , Demo , stack overflow , SystemC , System Design and Verification

Verification

Using the ARM Profiler with the Cadence Virtual System Platform

I have posted a new article over at blogs.arm.com covering the current integration…

• less than a min read
Virtual System Platform , virtual platforms , ARM Profiler , virtual prototypes , proflling , software , System Design & Verification , ARM

Verification

Image Gallery: Cadence-Denali Party at DAC 2011 in San Diego

The 20nm roadmap . TSMC reference flow 12 . The UVM 1.1 release . Verification IP…

• 1 min read
gallery , DAC , uvm , ACE , Joe Hupcey III , ABV , images , Functional Verification , Cadence VIP portfolio , formal , VIP , 20nm , EDA360 , TSMC , Denali Party , EDA , ADS , Denali , party , assertions , ARM , Assertion-Driven Simulation , Formal verification , Assertion-based verification

System, PCB, & Package Design 

Robert Hanson and Cadence Co-Host Signal Integrity Event in Massachusetts

In response to the OrCAD and Allegro 16.5 product release, and the growing demand…

• 1 min read
Allegro 16.5 , OrCAD PCB SI , Allegro PCB SI

Verification

DAC Cheesy Must See List: Enterprise Manager

Understandably, EDA industry observer John Cooley had to edit down all the submissions…

• 1 min read
Functional Verification , Metric Driven Verification , Enterprise Manager , MDV

Verification

DAC Preview: The Complete Incisive Enterprise Verifier Submission to John Cooley…

Understandably, EDA industry observer John Cooley had to edit down all the submissions…

• 1 min read
DAC , Joe Hupcey III , ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , EDA , Incisive , ADS , Tom Anderson , SVA , Chris Komar , PSL , assertions , gadfly , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verification

DAC Preview: Make Assertions Come Alive with Assertion-Driven Simulation

While Assertion-Based Verification (ABV) has been around for many years, ABV has…

• 2 min read
DAC , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , formal , ADS , Tom Anderson , SVA , Chris Komar , PSL , assertions , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Analog/Custom Design

SKILL for the Skilled: Virtuoso Applications of SKILL++

In this posting, I continue looking at applications of SKILL++. In particular, I…

• 4 min read
Team SKILL , Virtuoso IC6.1.5 , closures , IC 6.1.5 , sort , Virtuoso , Lisp , Custom IC Design , SKILL++ , sorting , SKILL

Verification

OVM 2.1.2 -- Getting You Ready for UVM

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM…

• 1 min read
SystemVerilog , DAC , uvm , OVM , Incisive , OVM SV , Funcional Verification , Accellera VIP TSC , IES , OVMWorld , OVM 2.1

System, PCB, & Package Design 

What's Good About Allegro Embedded Components? SPB16.5 Has Many New Enhancements

The Allegro 16.5 release was made available on May 17, 2011! This release adds additional…

• 5 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , Constraint-driven PCB Design flow , embedded components , DDR3 SoC Realization , IC Packaging , PDN , EDA360 , High Speed , Allegro Design Workbench , Library flow , Allegro 16.5 , Library and design data management , Power Delivery Network , PCB Editor , Design Entry HDL , Layout , design data management , design , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , Librarians , library , PCB Capture , DDR3 , Allegro

Digital Design

Five-Minute Tutorial: Avoiding The Use Of FILL1 Cells

A new thing that we're seeing with some 45nm libraries is the rule that single-wide…

• 2 min read
EDI , fill1 , filler cells , encounter , 45nm , checkFiller , Digital Implementation , Placement

System, PCB, & Package Design 

Miniaturization Through Embedding Packaged Components – Part2

This blog was written by a guest blogger – Mark Beesley of AT&S. His company is…

• 2 min read
embedded components , AT&S , embedded die in laminate , ECP , TeamAllegro , PCB Editor , miniaturization , Beesley , "PCB design" , SPB16.5 , Allegro PCB Editor , microvia , Allegro

Verification

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

It's been an exciting month for the System Realization team with the announcement…

• 2 min read
Virtual System Platform , TLM 2.0 , virtual prototype

Verification

Blazing a Trail With Ubuntu

One of the most popular blogs I wrote is running Incisive on Ubuntu . I have had…

• 3 min read
SystemC debugging , Virtual System Platform , debug , Ubuntu , SystemC , debugging , linux , System Design and Verification

Analog/Custom Design

CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

We have been talking about low power simulation and the Common Power Format (CPF…

• 2 min read
Low Power , CPF , Verilog-AMS , analog , Mixed-Signal , Spectre , Connect Module , mixed signal , wreal , SPICE

Verification

A Look at the Ongoing Functional Verification Seminar Series

Being a Marketing guy, one thing that I really enjoy is getting on the road for…

• 2 min read
Functional Verification , formal , Incisive , Mixed-Signal , metric-driven verification , MDV , IEV , IFV

Digital Design

Tab Completion with Encounter's dbGet Command: Smarter Than You Might Think

If there's one thing that makes navigating a UNIX command line or tool console more…

• 1 min read
dbGet , tab completion , screencast , encounter , Digital Implementation , Encounter Digital Implementation

Digital Design

Five-Minute Tutorial: Fixing SI Victim Nets

It's hard to believe there was a time when we didn't even run signal integrity analysis…

• 2 min read
SI , EDI , SI victim nets , SI analysis , NanoRoute , encounter , victim nets , Signal Integrity , Digital Implementation , five minute

System, PCB, & Package Design 

Cadence OrCAD Capture Marketplace -- The Cool Factors

Hey, did you hear about the new Cadence OrCAD Capture Marketplace? It has the first…

• 2 min read
PCB , Marketplace , on-line store , OrCAD Capture Marketplace , applications , Capture CIS , OrCAD online store , Team OrCAD , OrCAD , apps
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