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Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は、Honda総合研究センター/HGRに掲載された記事を、同社の許諾を得て転載しています。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Verification

Editor For OVM Field Registration Macros

The OVM SystemVerilog Class Library has built-in automation for many service routines…

• 1 min read
SystemVerilog , eclipse , uvm , Functional Verification , OVM , AMIQ , macros

Verification

DVCon: Showcasing The Cadence Passion For Verification Excellence

Yeah, I know I'm a marketing guy but I really like this stuff! For sure, we are going…

• 1 min read
SystemVerilog , uvm , Low Power , ABV , Functional Verification , simvision , OVM , Incisive , e , DVcon , SystemC , mixed signal , IES

Verification

Quiet Before The Storm? And What to Expect at DVCon 2010

In the last couple weeks Mentor did an about-face and decided to embrace SystemC…

• 1 min read
System Design and Verification , DVcon , SystemC , ESL

Digital Design

User Review of The Encounter Foundation Flow

This is a guest post from John McGehee. John is an independent consultant in Silicon…

• 4 min read
Foundation Flow , Encounter Digital Implementation System 9.1 , scripting , Encounter Digital Implementation System 8.1

Verification

Rev 2 of OVM e Scoreboard on OVMWorld.org Now

Just in time for DVCon 2010 , I'm happy to inform you that revision 2 of the OVM…

• less than a min read
Functional Verification , OVM , OVM e , e , DVcon

Verification

Moving Past The Missing Model Syndrome

One of the issues that has hindered the progress of using Virtual Platforms for early…

• 4 min read
Fast Models , Models , virtual platform , C-to-Silcon , SoC , ARM , System Design and Verification

System, PCB, & Package Design 

What's Good About The ADW Library Flow? ADW16.3 Has Many New Enhancements!

There are plenty of new enhancements to the Allegro Design Workbench (ADW) solution…

• 3 min read
DBeditor , SPB 16.3 , Library flow , Allegroro , PCB design , ADW 16.3 , ADW

Verification

Cadence Exec: Why Cadence is Comitted to e/Specman

In case you or your management are wondering about Cadence's commitment to supporting…

• less than a min read
IEEE 1647 , SystemVerilog , IntelliGen , Specman , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , e , team specman , OOP , ClubT , Aspect Oriented Programming , SystemC , eRM , Incisive Enterprise Simulator (IES) , AOP , IES-XL , Trailblazer

Verification

OVM Community Contributions: Wildly Popular And Clearly Essential

A couple of weeks ago, before going to bed one night I checked the statistics for…

• 2 min read
uvm , Verification methodology , Functional Verification , OVM , Contributions , Accellera

Verification

DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification…

• 4 min read
SystemVerilog , Specman , TLM , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , Incisive , e , Mike Stellfox , DVcon , OOP , AMIQ , SystemC , MDV , eRM , AOP , IES-XL

System, PCB, & Package Design 

Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

IBIS is sometimes known as the bird of knowledge, but is also the popular standard…

• 1 min read
PCB , SigXP UI , PCB Signal and power integrity , SPB 16.3 , IBIS-AMI , SerDes , PCB design

System, PCB, & Package Design 

What's Good About ASA Schematics? Numerous Improvements in The SPB16.3 Release!

Allegro System Architect (ASA) also known as System Connectivity Manager (SCM) allows…

• 1 min read
SCM , SPB 16.3 , Allegro 16.2 , ASA , PCB design , Schematic

Verification

Beyond Coverage: Adding Arbitrary Metrics To Your Metric-Driven flow

The most common metrics used in current metric driven verification (MDV) flows are…

• 3 min read
Specman , metric driven verification (MDV) , Functional Verification , vPlan , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be…

• 4 min read
High-Level Synthesis , Verification planning and management , TLM-driven design , TLM , System Design and Verification , embedded software , virtual protoype , ESL handoff , SystemC , C-to-Silicon Compiler , TLM 2.0-driven design , verification

Verification

An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week…

• 2 min read
Specman , Funcional Verification , IES-XL

System, PCB, & Package Design 

What's Good About DEHDL Font Support? The Secret's in The SPB16.3 Release!

Well - it's here! Native font support in Allegro Design Entry HDL (DEHDL)! This has…

• 8 min read
DEHDL , SPB 16.3 , Allegroro , PCB design , Design Entry , File Directives

SoC and IP

What’s on the Horizon for NAND and DRAM?

Young Choi , Guest Blog for Denali Software January is a time where lots of…

• 4 min read

Verification

What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology…

Cadence is in the vanguard of a movement to a higher level of productivity via the…

• 3 min read
TLM , RTL , System Design and Verification , IP re-use , Synthesis , verification
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