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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

Verification

Write Right OVM Verification Components

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes…

• 4 min read
SystemVerilog , OVM ML , OVM e , OVM SV , OVMWorld

Analog/Custom Design

Things You Didn't Know About Virtuoso: Search Assistant

People say I have strong google-fu . Whether it's finding information on a homework…

• 3 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

SoC and IP

NAND Forward Price Drops will Slow Significantly

Author's Note and Errata: There were some errors in the forward NAND pricing in the…

• 9 min read

Digital Design

How To: Create a Self-Contained Testcase in Encounter

In the course of performing design work in Encounter, it frequently becomes desireable…

• 2 min read
Digital Implementation forums , How To , testcase , Encounter Digital Implementation System 8.1

RF Engineering

RF Measurement Library: Capturing Circuit Characterization Setups on the Schemat…

Another design approach that Cadence supports that may not be obvious to all users…

• 1 min read
Circuit simulation , RFIC , custom design , RF design , design framework , RF Measurement library

Verification

TLM-Driven Design and Verification Solution

At this week's CDNLive! Japan we made an important press release announcement about…

• 2 min read
TLM-driven design , Calypto , Incisive , System C , TDM , C-to-Silicon , ARM , System Design and Verification

System, PCB, & Package Design 

What's Good About ABIML in PCB SI? It's in SPB16.2!

First - ABIML is an acronym for A lgorithm- B ased I nterconnect M odel L ibrary…

• 3 min read
SI , SPB 16.2 , ABIML , PCB design , Allegro

Verification

Tips on Using e Macros to Raise Abstraction and Facilitate Reuse

[Please welcome Yuri Tsoglin of Specman R&D to the guest blogging rostrum.] …

• 5 min read
IEEE 1647 , Specman , Functional Verification , tech tips , e , team specman , macros , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Embedded Software Plays an Important Role in Low Power Design

At Cadence, there is a big focus on low power design . In the mobile world, power…

• 3 min read
android , System Design and Verification , Low power verification and analysis , google , power forward , metric-driven verification , Incisive Software Extensions

Verification

Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

Some background info: Taking a quick look at Power dissipation in CMOS: …

• 3 min read
Low Power , Real Value Modeling , Functional Verification , Advanced Node , wreals , Mixed-Signal , Signal Integrity , verification

SoC and IP

Low-Power Memory Subsystems Imperative

The figure below was put forth at the recent Denali MemCon, in a speech by Samsung…

• 6 min read

Verification

AOP Discussion on LinkedIn

Hello All, Last week over in the LinkedIn Design Verification Professionals group…

• 3 min read
Specman , Functional Verification , OVM , e , AOP

Digital Design

Using A Dual Flop Methodology for Dynamic Power Savings

Imagine this scenario: Your chip is a low power design. You’ve used everything in…

• 1 min read
Low Power , dual flop , Digital Implementation

Analog/Custom Design

Things You Didn't Know About Virtuoso: The View From Above

A few years ago I bought a wonderful book called "Earth From Above". An amazing French…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso Layout Suite L , Virtuoso , VLS L , Custom IC Design

SoC and IP

Denali MemCon: Huge Hit in a Tough Market

Denali's 2009 Edition of MemCon, its Annual Storage and Memory-Only Conference held…

• 6 min read

Verification

Cadence System Design and Verification at DAC 2009

Traditionally in Cadence Marketing there were always two major events you really…

• 5 min read
DAC , System Design and Verification , schedule , C-to-Silicon , ESL handoff , SystemC , ARM

Verification

Another New Blog on e/Specman

Specmaniacs rejoice: there is a new blog centered around verification with e /Specman…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Industry Standard SystemC is What Designers Want

This past Monday saw not one HLS related announcement but two...this space is really…

• 2 min read
ANSI-C , C-to-Silicon , SystemC , HLS , System Design and Verification

Verification

Inside Cadence: Food for Charity & Freedom

Earlier today at the Cadence San Jose campus, a charity event was held off-cycle…

• 2 min read
Functional Verification , festival , Stars&Strikes , charity benefit
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