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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

定制IC芯片设计

Virtuoso: 新序曲—设计意图工具（Design Intent）工具简介

简化设计目标， 并且给版图设计师们提供更多自由来实现他们的设计目标。

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso Design Intent , Virtuoso Schematic XL , Layout design , Constraints , Custom IC Design , Custom IC , Schematic , Virtuoso Layout Suite XL

Verification

Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much…

One animation video - Patch Like The Wind - is worth a thousand words :) If you…

• 2 min read
Specman , Specman/e , Functional Verification , Specman e , tech tips , e language , team specman , save and restart

Breakfast Bytes

Google's Titan: How They Stop You Slipping a Bogus Server into Their Datacenter

At the recent HOT CHIPS conference, Scott Johnson of Google talked about some challenges…

• 6 min read
security , titan , google , supply chain , secure boot

Analog/Custom Design

Virtuosity: New Virtuoso Visualization and Analysis RAK for IC6.1.8/ICADVM18.1

We've updated the Virtuoso Visualization and Analysis Rapid Adoption Kit (RAK) for…

• 2 min read
ICADV12.3 , ICADVM18.1 , Rapid Adoption Kit , RAK , virtuoso visualization and analysis , ViVA , IC6.1.7 , IC6.1.8

Academic Network

Great Academic Networking in Taiwan - 2018 VLSI Design/CAD Symposium

Cadence Academic Network and Taiwan Marketing co-supported the annual VLSI Design…

• 1 min read
VLSI , university , Taiwan , Cadence Academic Network , Academic Network

The India Circuit

Don't Miss These 6 Things At CDNLive India 2018!

1. The Cadence keynotes: Lip-Bu Tan on Day 1 and Babu Mandava on Day 2 Apart from…

• 2 min read
CDNLive India , Babu Mandava , CDNLive , Cadence India , Lip-Bu Tan

定制IC芯片设计

Virtuoso: 新序曲-DRD推出新界面

最近几个月如果您关注Cadence 新闻的话，肯定听说了DRD重新推出的消息。让我们近距离来了解一下全新的DRD吧！

• less than a min read
Chinese blog , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , DRD , New in EDA , Custom IC Design , Custom IC

Breakfast Bytes

Carbon Nanotube Memory: Too Good to Be True?

One of the sessions at HOT CHIPS is on new technologies, and one of those presentations…

• 5 min read
Memory , cnt , carbon nanotube , DRAM , hot chips , nram

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural…

• less than a min read
Whiteboard Wednesdays , neural networks

Breakfast Bytes

What's For Breakfast? Video Preview September 3rd to 7th 2018

https://youtu.be/ipUI2OaAWX4 \ Coming from the old Ambit Design Systems office on…

• less than a min read
chiplets , ambit , buildgates , pcast , eri , darpa , chips

Breakfast Bytes

ImageNet: The Benchmark that Changed Everything

I like to date technical transitions from specific events, even though realistically…

• 6 min read
imagenet , gtsdb , Tensilica , CNN , neural network

Verification

Evolution of DisplayPort

In 2006, the Video Electronics Standards Association (VESA) designed a new display…

• 2 min read
Verification IP , DisplayPort , verification

Analog/Custom Design

Virtuoso: The Next Overture: Prelude to Cadence Virtuoso "Symphony No. 18.1"

Cadence Virtuoso is soon presenting a new symphony..."Symphony No. 18.1". Stay tuned…

• 1 min read
Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , New in EDA , Custom IC Design , Design Planner , Custom IC

Verification

Tales From DAC: Netspeed and the Cadence Interconnect Workbench Pair Up

Services like facial detection, efficient cloud server workload management, artificial…

• 2 min read
cadence IWB , Interconnect Workbench , Functional Verification , gemini , netspeed

Breakfast Bytes

Sanjay Goes to Europe via Texas

While I was in Germany recently, I sat down with the head of Cadence EMEA (Europe…

• 5 min read
Automotive , cadence europe , cadence emea

System, PCB, & Package Design 

EE Thermal 101 – Thermal basics for Electrical Engineers (Part 4 of 4)

In part 3 of this series, we used the concept of thermal resistors to develop a thermal…

• 6 min read
EE Thermal , temperature , Thermal Basics , Heat transfer , PowerDC

PCB、IC封装：设计与仿真分析

CDNLive日本：第四次工业革命与三维世界

7月20日在CDNLive日本站，Cadence公司资深副总裁、兼定制IC芯片和 PCB事业部总经理Tom Beckley发表了主题演讲“实现第四次工业革命（工业4…

• 1 min read
热 , Chinese blog , 电源完整性 , 热分析 , 3D Workbench , CDNLive , 工业革命4.0 , 中文 , Sigrity , 信号完整性 , Sigrity最新版 , 多板系统

Breakfast Bytes

Crossing the Chasm: Hogan Interviews Amit Gupta

The ESD Alliance will host another of its startup evenings with Jim Hogan, entitled…

• 7 min read
semi , amit gupta , Jim Hogan , esd alliance , solido

Breakfast Bytes

What's For Breakfast? Video Preview August 27th to 31st 2018

https://youtu.be/hxqDm1EAS7M \ Coming from the flagpoles in front of building 5…

• less than a min read
chiplets , openroad , eri , darpa , chips
CDNS - Fix Layout Hompage