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Breakfast Bytes

Arm TechCon: Get Ready for the NEOVERSE

I don't know if it was the vibe Arm's marketing was going for, but if you wanted…

Paul McLellan 23 Oct 2018 • 5 min read

ARM Techcon , softbank , arm neoverse , ARM

Breakfast Bytes

The World's First Working 7nm 112G Long Reach SerDes Silicon

At the start of November last year, Cadence announced that it was acquiring nusemi…

Paul McLellan 22 Oct 2018 • 6 min read

pam4 , 112g , semiconductor IP , SerDes , 7nm , datacenter

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之8：过孔结构——下一代高速布线解决方案

过孔转换对信号布线来说十分常见。在高速设计中过孔转换是造成PCB互连中信号衰减的主要原因。而且高速通道需要地孔临近关键信号，在信号走线换层时，提供连续的回流路径…

TeamAllegro 19 Oct 2018 • less than a min read

PCB , SI , Chinese blog , Allegro 17.2 , PCB设计 , 差分对支持 , 中文 , 信号完整性 , Allegro升级17.2 , SI分析与建模 , 高速 , 差分对

System, PCB, & Package Design

How is a Multi-board PCB System Assembly Different from Rigid-Flex Assembly

When people typically think of multi-board PCB design, they tend to picture racks…

TeamAllegro 19 Oct 2018 • 4 min read

multi-board , multi-board systems , multiboard PCB , HighSpeed , multiboard , PCB design , multiboard systems , Allegro

Breakfast Bytes

The DARPA Electronic Resurgence Initiative (ERI)

Many weeks ago DARPA organized a summit at the Palace of Fine Arts in San Francisco…

Paul McLellan 19 Oct 2018 • 8 min read

openroad , magestic , idea , posh , eri , darpa

Analog/Custom Design

Virtuoso IC6.1.8 and ICADVM18.1 Now Available

The IC6.1.8 and ICADVM18.1 production releases are now available for download. To…

Virtuoso Release Team 18 Oct 2018 • 5 min read

Analog Design Environment , ICADVM18.1 , ADE Explorer , ADE , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Virtuoso: The Next Overture , Custom IC Design , Custom IC , IC6.1.8

Breakfast Bytes

CDNLive Israel 2018

This week it was the last CDNLive of the year, CDNLive Israel in Tel Aviv. From my…

Paul McLellan 18 Oct 2018 • 5 min read

Breakfast Bytes

Jasper User Group 2018

This week it is CDNLive Israel. But last week it was Jasper User Group (JUG). At…

Paul McLellan 17 Oct 2018 • 8 min read

Jasper User Group , formal , formal signoff , JasperGold , Formal verification

Digital Design

What's in it for Me in Innovus 18.10 Release?

At advanced nodes, there’s always a deep conflict between power, performance, and…

MJ Cad 16 Oct 2018 • 1 min read

Digital Implementation forums , Tempus , Release Page , Cadence Online Support , Digital Implementation , Innovus , full flow , blog

Breakfast Bytes

Of Arms and the Man I Sing

Arma virumque cano—of arms and the man I sing. This is the famous opening line of…

Paul McLellan 16 Oct 2018 • 6 min read

ARM Techcon , arm datacenter , hpe , xcelium , ARM , JasperGold , verification

Verification

Learn How Valens uses Specman Macros Automate Configuration of Verification Environments…

Valens has achieved success through applying Specman to their verification projects…

Steve Brown 16 Oct 2018 • less than a min read

verification

System, PCB, & Package Design

Real World (Unexpected) Examples of Multi-Board PCB Systems

What do reusable rockets, self-driving cars, and the blockchain have in common? Besides…

TeamAllegro 16 Oct 2018 • 4 min read

multi-board pcb system , multi-board , system architecture design , system level design , PCB system design , electronic system , system simulation , multiboard , system architect software , multiboard pcb system , elecronic system design