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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Breakfast Bytes

TSMC Technology Roadmaps

TSMC had their annual Technology Symposium last week. As always, my post comes with…

• 6 min read
Automotive , n5 , IoT , TSMC , HPC , n7 , mobile , n10

Academic Network

The Worldwide MEMS Design Contest Officially Starts

Cadence, X-FAB, Coventor and Reutlingen University have Selected 10 Design Teams…

• 2 min read
Cadence Academic Network , X-FAB , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Mixed-Signal , Coventor

Breakfast Bytes

CDNLive Silicon Valley Preview

Yes, it's that time of year again. Just like a cat has nine lives, Cadence has nine…

• 2 min read
microsoft , CDNLive , Santa Clara Convention Center , CDNLive Silicon Valley

Breakfast Bytes

Dracula, Vampire, Assura, PVS: A Brief History

Cadence was created from the merger of SDA and ECAD, as you probably know. SDA had…

• 9 min read
Extraction , Dracula , DRC , vampire , design rule check , Assura

Breakfast Bytes

Andy Bechtolsheim Keynote on the Future of Networking

At the recent Linley Cloud Hardware Conference, the keynote was given by Andy Bechtolsheim…

• 7 min read
andy bechtolsheim , arista networks , andreas bechtolsheim , linley cloud hardware conference , Linley

Breakfast Bytes

TSMC Announces New 12FFC Process

Today at the TSMC Technology Symposium, Cliff Hou, TSMC's VP of R&D, is set to announce…

• 4 min read
Design IP , 12FFC , TSMC , TSMC Technology Symposium , 12nm , InFO , 7nm

Breakfast Bytes

What's For Breakfast? Video Preview March 20th to 24th 2017

https://youtu.be/Qm8epP4YobA Coming from TSMC Technology Symposium, Santa Clara…

• less than a min read
Léman Micro Devices , CDNLive , SDE , 12FFC , TSMC , TSMC Technology Symposium , InFO , mobile , blood pressure , system design enablement , 7nm , Smartphone

Analog/Custom Design

Virtuoso Video Diary: Real-Time Tuning—A Lot More Than Just an Assistant!

Have you ever found yourself in situations where you’re not sure which values of…

• 3 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design

Whiteboard Wednesdays

Whiteboard Wednesdays - Display Stream Compression: Higher Display Resolutions in…

In this week's Whiteboard Wednesdays video, Alex Passi takes a closer look at Display…

• less than a min read
mobile devices , Whiteboard Wednesdays , MIPI , MIPI protocols

Breakfast Bytes

Cadence at MWC: Does This Headset Make Me Look Silly?

Cadence has attended MWC ever since it acquired Tensilica, and they attended for…

• 4 min read

Digital Design

Have DRC Tools Run Out of Steam? – Part 1

In the EDA history of design rule check (DRC), there have been two distinct eras…

• 3 min read
Physical verification , DRC , design rule check

Breakfast Bytes

ESD Alliance Panel on Energy Policy for the IoT Era

BREAKING NEWS: I just received an email that the panel I wrote about here has been…

• 4 min read
california energy commission , energy policy , ESDA , IoT , Internet of Things , san jose city hall , cec , esd alliance

Verification

Static Members in e

How do you define elegant or clean code? Usually, you know it when you see it; defining…

• 9 min read
Specman , Incisive , e language , static , xcelium , verification

Breakfast Bytes

Reliability in Monterey: a Preview of IRPS

The major conference on semiconductor reliability is the International Reliability…

• 4 min read
international reliability and physics symposium , Intel , IBM , Monterey , irps , NASA , reliability

Breakfast Bytes

GF Silicon Photonics: Fiber Attach Is the Secret Sauce

A lot of constraints in datacenters are fixed even though others are increasing.…

• 5 min read
fiber attach , linley group , linley cloud hardware conference , silicon photonics , GlobalFoundries

Analog/Custom Design

Virtuoso Video Diary: Noise Simulation in Spectre RF Using Improved Pnoise/Hbnoise…

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM…

• 4 min read
Spectre RF , noise simulation , Virtuoso , Virtuoso Video Diary

Breakfast Bytes

MWC: The Future of Mobile: Part 2

This is the second of a two part post about the future of mobile, long-term dreams…

• 9 min read
softbank , veon , at&t , gsma , Mobile World Congress , ARM

SoC and IP

Memory Trends for Automotive Markets

Remember automobiles from a few years ago? They were pretty simple machines with…

• 4 min read
Design IP , IP , Memory , LPDDR4 , LPDDR , DIP , memory IP , Design IP and Verification IP , memories

Whiteboard Wednesdays

Whiteboard Wednesdays - Eliminate the Memory Bottleneck with Universal Flash Sto…

In this week's Whiteboard Wednesdays video, Ofir Michaeli discusses Universal Flash…

• less than a min read
Whiteboard Wednesdays , UFS
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