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The Art of Analog Design Part 4: Mismatch Analysis

In Part 3 , we started to explore how to analyze the results of Monte Carlo analysis…

Art3 15 Oct 2017 • 3 min read

spectre aps , Analog Design Environment , Virtuoso Variation Option , mismatch analysis , Analog Simulation , Monte Carlo , Custom IC Design

Analog/Custom Design

The Art of Analog Design Part 5: Mismatch Analysis II

In Part 4 of the series, we looked at applying mismatch analysis as a design tool…

Art3 13 Oct 2017 • 3 min read

spectre aps , offset voltage , mismatch analysis , Analog Simulation , ADE , Monte Carlo analysis , Strong Arm latch , dynamic comparator

Verification

Teradyne Standardizes on Xcelium Simulator

Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator…

XTeam 13 Oct 2017 • less than a min read

Teradyne , ASIC , press release , xcelium , JasperGold , vManager

Verification

Teradyne "Formally" Adopts JasperGold FPV

CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation…

XTeam 13 Oct 2017 • 2 min read

Teradyne , FPV , CDNLive , customer success , JasperGold , Formal verification

Analog/Custom Design

Virtuosity: Can I Speed up My Plots?

If your Virtuoso ® ADE Assembler, Virtuoso ® ADE Explorer or Virtuoso ® ADE XL setup…

AdityaMainkar 13 Oct 2017 • 3 min read

Analog Design Environment , ADE GXL , ADE Explorer , Explorer , ADE XL , analog , license , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuosity , mixed signal , Custom IC Design , ADE Assembler

Breakfast Bytes

Rowen on Vision, Innovation, and the Deep Learning Explosion

The keynote for the second day of the Linley Processor Conference was by Chris Rowen…

Paul McLellan 13 Oct 2017 • 5 min read

Chris Rowen , deep learning , linley processor conference , deeplearningmachinelearning , Computer Vision , Tensilica , vision , neural networks , Breakfast Bytes

Verification

Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AM…

It’s been quite a long 5-year journey building and deploying Performance Analysis…

Steve Brown 12 Oct 2017 • 2 min read

iwb , interconnect , amba5 , Interconnect Workbench , Palladium , Performance Analysis , AMBA , CoreLink , xcelium , ARM

Computational Fluid Dynamics

Aerodynamic Simulation of a NASA Common Research Model (CRM) Aircraft for JAXA APC…

Born through the merger of three previously independent organizations on October…

AnneMarie CFD 12 Oct 2017 • 5 min read

Breakfast Bytes

Linley Gwennap on the Microprocessor Market

Linley Gewennap always gives the opening keynote for the Linley Microprocessor Conference…

Paul McLellan 12 Oct 2017 • 6 min read

Automotive , Intel , risc-v , linley processor conference , deeplearningmachinelearning , processor , AMD , linley group , IoT , Tensilica , Internet of Things , ADAS , ARM , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview October 16th to 20th 2017

https://youtu.be/CUabZn_-1_M Coming from a cartoon world (camera Sean) Monday…

Paul McLellan 11 Oct 2017 • less than a min read

metric driven signoff , Metric Driven Verification , AMD , semi , vishal kapoor , sjsu , Jim Hogan , strategic materials conference , Oski , Formal verification

Breakfast Bytes

The Rise of the China IC Industry

At the SEMI Strategic Materials Conference, SMC, Lung Chu, who heads up SEMI China…

Paul McLellan 11 Oct 2017 • 5 min read

IC , SEMI China , China , semicon china , Lung Chu , SEMI Strategic Materials Conference , smc , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Automotive Memory Trends and Technologies

In this week's Whiteboard Wednesdays, the first in a three-part series, Scott Jacobson…

References4U 10 Oct 2017 • less than a min read

Automotive , Whiteboard Wednesdays , NAND flash , automotive electronics , memory models

Breakfast Bytes

Grace Hopper Celebration of Women in Computing

Last week was the Grace Hopper Celebration of Women in Computing (GHC), held in Orlando…

Paul McLellan 10 Oct 2017 • 6 min read

women in computing , grace hopper , telle whitney , anita borg institute , Breakfast Bytes

Learning and Support

Shorten Your Time to Market! Get Started with Training Bytes

How can you become an expert in your field? Access our short self-help videos called…

wandia 9 Oct 2017 • less than a min read

videos , Self Learning , Support , training bytes

Breakfast Bytes

Logical Equivalence Checking to Get Smart

In the late 1960s and early 1970s, there was a TV show called "Get Smart." It was…

Paul McLellan 9 Oct 2017 • 5 min read

conformal lec , cdnlive korea , logical equivalence checking , LEC , conformal smart lec , Breakfast Bytes

Breakfast Bytes

Computational Origami

At the recent Decoding Formal Club meeting, organized by Oski and sponsored by Cadence…

Paul McLellan 6 Oct 2017 • 4 min read

computational origami , robert lang , origami , Breakfast Bytes , Formal verification

Digital Design

Faster and Smarter

At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about…

FormerMember 5 Oct 2017 • 1 min read

cdnlive korea , deep learning , CDNLive , machine learning , digital , signoff

Analog/Custom Design

Virtuosity: Power Filtering!

Finally, we have filters in the Corners Setup form, Results tab, Outputs tab, Data…

Arja H 5 Oct 2017 • 2 min read

Analog Design Environment , ADE Explorer , Filtering , ADE , Virtuoso Analog Design Environment , Analog Design Environment , ADE Assembler

Breakfast Bytes

EDPS: The Remains of the Day

EDPS is the Electronic Design Process Symposium, historically held in Monterey, but…

Paul McLellan 5 Oct 2017 • 12 min read

deep learning , electronic design process symposium , EDPS , Test , machine learning , design , Breakfast Bytes

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