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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Breakfast Bytes

DAC: My Guide

DAC starts this weekend. So what should you go to? I'll tell you what my plans are…

• 3 min read
dac2016 , DAC , NVIDIA , Gary Smith EDA , Heart of Technology , Denali Party , dac53 , Cooley , 53dac

SoC and IP

DAC 2016—Drink from the Expert Bar and Then at the Denali Party

Black-belt interface and memory protocol technologists will be at your disposal at…

• 2 min read
DAC , IP , Denali Party , Denali

Verification

How to Maximize Your Verification Experience at DAC 2016

Next week will mark the annual EDA gathering in Austin. For me it is my 20th DAC…

• 13 min read
dac2016 , DAC , Verification Computing Platform , Protium , Palladium , Prtable Stimulus

Breakfast Bytes

ITF Keynote: IC Innovation—the Heartbeat of Yesterday, Today, Tomorrow

Luc van den Hove, the CEO of imec, gave the opening keynote at the imec Technology…

• 4 min read
Gordon Moore , neuromorphic computing , smart cities , IoT , system technology co-innovation , imec , itf brussels , Internet of Things , luc van den hove , moore's law , itf

Breakfast Bytes

Inside Secure Writes the Book on IoT Security for Dummies

At the Linley IoT conference recently, one of the presentations was by Steve Singer…

• 4 min read
security , data in use , data at rest , security for dummies , IoT , inside secure , Linley , iot security for dummies , data in motion , Breakfast Bytes , linley iot conference

Whiteboard Wednesdays

Whiteboard Wednesdays—Advantages of the MIPI I3C Interface

In this week's Whiteboard Wednesdays video, Alex Passi explains the advantages provided…

• less than a min read
mobile devices , Whiteboard Wednesdays , IP , MIPI , I3C

SoC and IP

16Gbps Multi-link, Multi-protocol SerDes at the 21st IEEE European Test Symposiu…

The 21 st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands…

• 1 min read
16gbps , PCIe Gen4 , SerDes , Multi-link , multi-protocol

Academic Network

DAC 2016—Student Activities and Scholarships

The Cadence Academic Network is the proud sponsor of all student activities and scholarships…

• 2 min read
DAC , Cadence Academic Network , dac53 , Design Automation Conference , 53dac

Analog/Custom Design

Virtuoso Video Diary: Tips and Tricks on Virtuoso Visualization and Analysis XL …

Virtuoso Video Diary is envisaged to be an online journal that will relay information…

• 6 min read
custom/analog , Analog Simulation , analog , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Breakfast Bytes

DAC: the Curtain Rises on the Cadence Theater

As in previous years, a highlight of the Cadence booth at DAC is the theater, where…

• 4 min read
DAC , Cadence Academic Network , Cadence Theater , dac53 , Design Automation Conference , 53dac

SoC and IP

What Memory Best Fits Your Application?

With highly effective DDR4 and LPDDR4 class memories, it’s not always easy to know…

• 1 min read
DDR4 , LPDDR4 , 4266 , 3200

Breakfast Bytes

Breakfast Bytes: Post #150

This is the 150th blog post here at Breakfast Bytes since I arrived at Cadence in…

• 3 min read
IP , EDA , Semiconductor , Breakfast Bytes

Breakfast Bytes

3D Xpoint: Is It a Game-Changer?

You have probably at least heard of 3D Xpoint. This is a memory technology jointly…

• 4 min read
Intel , Memory , Micron , flash , memory hierarchy , 3dx , DRAM , Breakfast Bytes , 3d xpoint

System, PCB, & Package Design 

What's Good About the Latest in ADW? The 16.6-2015 Release Has Several New Enhancements…

With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new…

• 2 min read
PCB , Cadence Design Systems , Allegro Design Workbench , Library and design data management , Grzenia , Librarians , library , ADW

Breakfast Bytes

Andrew Kahng on Industry-Academia Cooperation

At CDNLive Silicon Valley, Professor Andrew Kahng of UCSD gave a presentation titled…

• 4 min read
ucsd , Cadence Academic Network , CDNLive , academia , kahng , CDNLive Silicon Valley

SoC and IP

Continued Strength of the Design&Reuse IP-SoC India

Design&Reuse events are always exciting for their draw of an IP-centric audience…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes

Verification

Simulation Acceleration—Maximizing Simulator Performance

"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to…

• 4 min read
Specman , Functional Verification , e , specman elite , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Creating an Acceleration-Ready Simulation Environment with…

In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated…

• less than a min read
accelerated VIP , Verification IP , Whiteboard Wednesdays , IP , VIP , Palladium XP , simulation , SystemVerilog UVM , verification

Breakfast Bytes

CDNLive: Routing at 10nm

At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence…

• 3 min read
CDNLive , Routing , implementation , 10nm
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