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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Coherent Interconnect Verification Challenges

In this week's Whiteboard Wednesdays video, Nimrod Reiss discusses the challenges…

• less than a min read
Verification IP , Whiteboard Wednesdays , throughput , VIP , latency , snoop filtering , Nimrod Reiss , interconnect verification

Breakfast Bytes

Jeff Bier: When Every Device Can See

Jeff Bier is the founder of the Embedded Vision Alliance, which runs the annual Embedded…

• 3 min read
deep neural network , deep learning , Embedded Vision Alliance , machine learning , neural network , machine vision

Academic Network

EDA Workshop in Taiwan

Cadence Academic Network recently participated in the 2016 IEEE and CEDA Workshop…

• 1 min read
academic workshop , academia

Breakfast Bytes

What's For Breakfast? Video Preview February 20th to 24th 2017

https://youtu.be/EVZ4T8TPim8 Coming from inside a Microsoft Hololens Monday…

• less than a min read
holoens , DesignCon , spie advanced lithography , Mobile World Congress , MWC , rocketsim , target impedance , parallel simulation

Analog/Custom Design

Virtuoso Video Diary: Eye Masks

Have you ever plotted an eye diagram in Virtuoso Visualization and Analysis XL and…

• 4 min read
Eye Mask , Analog Design Environment , Eye , ADE GXL , ViVa-XL , ADE Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuoso Video Diary

Breakfast Bytes

The Second Embedded Neural Network Symposium

A couple of weeks ago, Cadence held the second embedded neural network symposium…

• 8 min read
deep neural networks , enns , dnn , embedded neural networks , neural networks

Breakfast Bytes

Integrated Bus Routing Solution

For most chips, the automatic routing in Innovus—NanoRoute—works well. But there…

• 3 min read
integrated bus routing solution , grid-based routing , analog , Innovus , high frequency router

Breakfast Bytes

Circuits and Systems for Security and Privacy

One of the perks of writing this blog is that I get offered review copies of interesting…

• 6 min read
security , side channel attacks , encryption , puf , crc press , random number , physically unclonable functions

Breakfast Bytes

Tom Quan on TSMC's Automotive Strategy

Tom Quan recently came to Cadence to talk about TSMC's automotive strategy. Tom and…

• 4 min read
Automotive , tom quan , TSMC , 7ff , 16FFC , ISO 26262 , ADAS , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview February 13th to 17th 2017

https://youtu.be/HL0GFG9tNP4 Coming from Cadence security camera Monday…

• less than a min read
deep learning , machine learning , convolutional neural networks , moore's law , embedded neural networks , neural networks , machine vision

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplify UVM Scoreboarding with Cadence VIP

In this week's Whiteboard Wednesdays video, principal AE Matt Diehl explains how…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , DisplayPort , Matt Diehl

Breakfast Bytes

He Who Goes First Loses, EDA Edition

Yesterday I wrote a post He Who Goes First...Loses about how being first isn't always…

• 4 min read
point tools , hunters , EDA , ambit , farmers

Breakfast Bytes

He Who Goes First...Loses

There is a saying, of course, that he who goes first wins. And sometimes, and in…

• 5 min read
apple pay , credit cards , m-pesa , tube , london tube

Breakfast Bytes

Handling Variability in the Modern Design Cycle

Igor Keller gave an internal presentation on Handling Variability in the Modern Design…

• 6 min read
on chip variation , AOCV , STA , OCV , variability , voltage droop , static timing , layout dependent effects , miller capacitance , SOCV , crosstalk , slew , SSTA

Verification

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

What's For Breakfast? Video Preview February 6th to 10th 2017

https://youtu.be/XOS4sfILahc Coming from Design Con 2017 Monday: He Who…

• less than a min read
security , Automotive , Routing , TSMC , business strategy , Innovus , privacy

Verification

IEEE Std 1647™ 2016 - e Language - New Standard Publication

Congratulations to the IEEE-1647 e Functional Verification Language Working Group…

• 2 min read
IEEE 1647 , Specman , e , e language , specman elite

Breakfast Bytes

The ASML Standard Node

One of the first posts I wrote here at Breakfast Bytes was Where Does 5 Really Mean…

• 3 min read
mmhp , cphp , standard node , EUV

Breakfast Bytes

The Book for Practicing Formal Verification Engineers

At the no-longer-so-recent Jasper User Group JUG last year, the keynote was by Erik…

• 3 min read
formal verification book , Formal verification
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