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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Breakfast Bytes

A Brief History of Cadence: the Present Day

In the early days, like all the larger EDA companies, Cadence grew through a mixture…

• 3 min read
cadence , startups , history , SDA , acquisitions

Breakfast Bytes

Blue Gecko, Designed with Cadence Mixed-Signal, Low-Power Flow

Blue Gecko is a system on chip (SoC) created by Silicon Labs to provide wireless…

• 1 min read
AMS , Tempus , Silicon Labs , blue gecko , Voltus , bluetooth , Spectre , Innovus , mixed signal , zigbee

Academic Network

Student Day at embedded world, Nuremberg

The Cadence Academic Network was proud to sponsor the Student Day at embedded world…

• 1 min read
Student Day , Cadence Academic Network , Embedded World

Breakfast Bytes

EDAC Becomes the Electronic System Design Alliance

Last night, Bob Smith, the executive director of what was EDAC, announced the new…

• 5 min read
robert smith , ESDA , semi , embedded software , bob smith , Semiconductor , semiconductor IP , EDAC , Breakfast Bytes , esd alliance

SoC and IP

Design IP Customer and Technology Presentations at CDNLive Silicon Valley, April…

We have an exciting Design IP track at CDNLive Silicon Valley again this year. ARM…

• 1 min read
Design IP , CDNLive , PCIe Gen4 , DIP , SerDes , Silicon Valley

Analog/Custom Design

Welcome to TeamADE

Welcome to the new home of all things related to the Virtuoso® Analog Design Environment…

• less than a min read
custom design , Virtuoso Analog Design Environment , Virtuoso , analog design

Breakfast Bytes

Memory Standards and the Future

I sat down and talked with Amjad Qureshi recently He is vice president of research…

• 3 min read
Memory , DDR4 , LPDDR4 , JEDEC , HBM , Denali , DDR , amjad qureshi

Whiteboard Wednesdays

Whiteboard Wednesdays - Memory Trends to Fit Your Application

In this week’s Whiteboard Wednesdays video, Jeffrey Chung talks about the progression…

• less than a min read
Design IP , LPDDR , memory IP , DDR

Breakfast Bytes

Encryption: Why Backdoors Are a Bad Idea

I have always had a passing interest in encryption and security. My PhD is on network…

• 7 min read
vlsi technology , imessage , Apple , clipper , encryption , iOS , granitephone , backdoor , Breakfast Bytes

System, PCB, & Package Design 

What's Good About the Latest System-In-Package (SiP)? New Capabilities in 16.6-2015…

Several new features have been added to the 16.6-2015 SiP release. Read on for more…

• 4 min read
IC Packaging and SiP Design , Cadence Design Systems , SiP , IC Packaging , Allegro 16.6 , Digital SiP design , Grzenia , Allegro

Verification

How to Handle a Binding Catastrophe

Are you busy debugging your environment topology and coming up against components…

• 3 min read
Specman , TLM , binding

Breakfast Bytes

A Brief History of Cadence: the Post-Costello Years

Through the 1990s, Cadence made lots of smaller acquisitions. In 1997, Joe Costello…

• 2 min read
Costello , cadence , Bingham , Lip-Bu Tan , mergers , history , fister , Harding

SoC and IP

Tech Shanghai Drives Innovation by Overcoming Challenges

Far more often than we imagine, we think about China within the context of the complicated…

• 2 min read
China , DDR4 , PCIe Gen4 , tech shanghai

System, PCB, & Package Design 

Reports – Now Sorting Your Strings the Way YOU Want Them Sorted

When it comes right down to it, if we asked most of you what was the most important…

• 4 min read
documentation , Cadence Design Systems , Reports , manufacturing exports , APD , Allegro Package Designer , IC packaging documentation , SiP Layout , sorting

Breakfast Bytes

Moore's Law Slowing? Don't Tell TSMC

TSMC is a manufacturing powerhouse. It has twice the capacity of any other non-memory…

• 4 min read
cycle time , hvm , gigafab , TSMC , 16FFC , n7 , n10 , 7nm , 10nm , days per layer , nanjing , Breakfast Bytes , volume ramp

Breakfast Bytes

CDNLive: It's Only Two Weeks Away

In two weeks time (or a fortnight as we say in Britain) is CDNLive Silicon Valley…

• 1 min read
packaging , CDNLive , custom design , Power Integrity , Mixed-Signal , Tensilica , Signal Integrity , Qualcomm , Digital Implementation , PCB design , front end design , signoff , GlobalFoundries , CDNLive Silicon Valley , power , System Verification

Verification

e Templates – Cool Tool, Now Even Cooler

One of the reasons why verification engineers love e is the power it gives them as…

• 3 min read

Breakfast Bytes

Andy Grove, RIP

Andy Grove, co-founder and long-time CEO of Intel, passed away on Monday. He was…

• 3 min read
Intel , only the paranoid survive , Fairchild , high output management , andy grove

Whiteboard Wednesdays

Whiteboard Wednesdays—Assertion-Based VIP

In this week's Whiteboard Wednesdays video, Tom Hackett takes a closer look at assertion…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , assertion-based VIP
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