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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Latest blogs

System, PCB, & Package Design 

Reports – Now Sorting Your Strings the Way YOU Want Them Sorted

When it comes right down to it, if we asked most of you what was the most important…

• 4 min read
documentation , Cadence Design Systems , Reports , manufacturing exports , APD , Allegro Package Designer , IC packaging documentation , SiP Layout , sorting

Breakfast Bytes

Moore's Law Slowing? Don't Tell TSMC

TSMC is a manufacturing powerhouse. It has twice the capacity of any other non-memory…

• 4 min read
cycle time , hvm , gigafab , TSMC , 16FFC , n7 , n10 , 7nm , 10nm , days per layer , nanjing , Breakfast Bytes , volume ramp

Breakfast Bytes

CDNLive: It's Only Two Weeks Away

In two weeks time (or a fortnight as we say in Britain) is CDNLive Silicon Valley…

• 1 min read
packaging , CDNLive , custom design , Power Integrity , Mixed-Signal , Tensilica , Signal Integrity , Qualcomm , Digital Implementation , PCB design , front end design , signoff , GlobalFoundries , CDNLive Silicon Valley , power , System Verification

Verification

e Templates – Cool Tool, Now Even Cooler

One of the reasons why verification engineers love e is the power it gives them as…

• 3 min read

Breakfast Bytes

Andy Grove, RIP

Andy Grove, co-founder and long-time CEO of Intel, passed away on Monday. He was…

• 3 min read
Intel , only the paranoid survive , Fairchild , high output management , andy grove

Whiteboard Wednesdays

Whiteboard Wednesdays—Assertion-Based VIP

In this week's Whiteboard Wednesdays video, Tom Hackett takes a closer look at assertion…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , assertion-based VIP

SoC and IP

TSMC’s Technology Symposium 2016 is the Place to be for Innovation

At this year’s Technology Symposium, TSMC disclosed that they will provide two N7…

• less than a min read
DDR4 , LPDDR4 , TSMC Tech Symposium , ip cores , PCIe , 16FF+

Breakfast Bytes

EDPS: Dolphins and FinFETs

The Electronic Design Process Symposium (EDPS) has been held in late April or early…

• 3 min read
Low Power , Electronic Design Process , multi-die , Monterey , EDPS , cyber security

Academic Network

Stratus High-Level Synthesis Is Available to Academia

To support academia using the latest industry-standard tools, Cadence's Stratus High…

• 1 min read
Cadence Academic Network , academia , Stratus , HLS

Breakfast Bytes

TSMC Technology Symposium: Process Status

At the recent TSMC Technology Symposium, various speakers gave details of the various…

• 6 min read
Automotive , specialty processes , IoT , TSMC , <7nm , InFO , 16FFC , n7 , n10 , Breakfast Bytes , 16FF+

Academic Network

Tensilica Day in Hanover

The idea to have a Tensilica Day at University of Hanover was born during CDNLive…

• 2 min read
Cadence Academic Network , Tensilica

SoC and IP

DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps

Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY…

• 1 min read

Breakfast Bytes

TSMC Technology Symposium: Four Strategic Markets

When Willie Sutton was asked by the judge why he kept robbing banks, he said "because…

• 3 min read
Automotive , IoT , TSMC , TSMC Technology Symposium , 7ff , 16ff , 10FF , 16nm , HPC , n7 , mobile , n10 , 7nm , 10nm , n16

Breakfast Bytes

Dark Silicon: Not a Character from Star Wars

Dark Silicon may sound like a character from the latest Star Wars movie, but it actually…

• 6 min read
Dennard scaling , Dark Silicon , moore's law , dennard , multicore

Breakfast Bytes

EDAC Becomes...You Have to Be There to Be the First to Know

When Bob Smith took over as the Executive Director of EDAC, I called him up and one…

• 2 min read
bob smith , EDA Consortium , EDAC , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Implementation of Higher Speed PCIe Gen4 IP

In this week's Whiteboard Wednesday's video, Gopi Krishnamurthy highlights how Cadence…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PHY IP , PCIe , PCI Express

Breakfast Bytes

The Economist on the End of Moore's Law

"The number of people predicting the end of Moore's Law doubles every two years.…

• 3 min read
Intel , The Economist , moore's law , FinFET

Breakfast Bytes

A Brief History of Cadence: The Solomon-Costello Era

Cadence has grown from a small startup to a $1.7B corporation. Its history includes…

• 3 min read
Jim Solomon , ECAD , Joe Costello , SDA

System, PCB, & Package Design 

Designing a New Component from Scratch Inside Your Layout Environment

Have you ever needed to build a component with a custom, complex pin pattern? Have…

• 6 min read
IC package design , APD , package design , Allegro Package Designer , SiP Layout , substrate design tools
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