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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays—Radar Signal Processing for Automotive Applications

In this week's Whiteboard Wednesdays video, the first of a two-part series, Pushkar…

• less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , radar , Tensilica

Breakfast Bytes

CDNLive Bengaluru, a Long Journey

I've not been to Bengaluru for about 20 years, when I ran engineering at Compass…

• 3 min read
CDNLive India , bengaluru , Cadence India , Breakfast Bytes

System, PCB, & Package Design 

Five Industry Experts Coming to CDNLive Boston to Discuss Signal and Power Integrity…

Who Are They? Istvan Novak – Senior Principal Engineer at Oracle Kevin Roselle…

• less than a min read
CDNLive , Signal Intregrity , Power Integrity , Boston , PCB design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Persistent Snap and Select? New Capabilities…

The 16.6-2015 Allegro PCB Editor release introduces a few new features that provide…

• 2 min read
PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor

Breakfast Bytes

What's for Breakfast? August 8th

This is the first weekly video "What's for Breakfast?" that previews the blog entries…

• 1 min read
risc-v , CDNLive India , CDNLive , preview , whats for breakfast? , cdnlive bengaluru , mobilemobile 5g , Breakfast Bytes

Breakfast Bytes

Breakfast Bytes Guide to Japan Travel

Cadence was shut down for the week of July 4th, so I went to Japan with a friend…

• 5 min read
tsukiji , kyoto , osaka , tourism , narita , kansai , japan , travel , haneda

Breakfast Bytes

Merger Mania

At the recent GSA Silicon Summit at the Computer History Museum in Mountain View…

• 6 min read
Wally Rhines , merger mania , gsa silicon summit , mergers , gsa , Breakfast Bytes , acquisitions , Mentor

Breakfast Bytes

Chipworks Looks at Smartphones

Chipworks buys hundreds of devices every year and strips them down to look at the…

• 4 min read
Intel , Apple , Samsung , TSMC , Linley , wearables , mobile , GlobalFoundries , smartphones , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Using Processor Clusters to Implement Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen describes how to use processor…

• less than a min read
Whiteboard Wednesdays , IP , processor clusters , Tensilica , neural networks , CNN

SoC and IP

Fastest Octal SPI Flash Interface Available Now From Cadence

Flash memory is being utilized in computers and electronic devices found in Automotive…

• 1 min read
PHY , octal spi , spi , nor flash

SoC and IP

Cadence at Flash Memory Summit 2016: Octal SPI, eMMC 5.1, ONFi 4, and Tensilica SSD…

If you design with flash memory components or IP solutions, head on over to the Santa…

• 1 min read
Verification IP , Design IP , Memory , VIP , Tensilica , semiconductor IP , Design and Verification IP , Design IP and Verification IP , memories

Breakfast Bytes

Smartphones: Linley's Annual Review

Last week was the Linley Mobile Conference, although it is now the Mobile and Wearables…

• 3 min read
Apple , Samsung , wearables , mobile , Smartphone , Huawei

Analog/Custom Design

Virtuoso Variation Option: Reliable High-Yield Design with Scaled-Sigma Sampling

What’s Scaled-Sigma Sampling? Scaled-sigma sampling (SSS) is an efficient algorithm…

• 4 min read
Variability Aware Design , scaled sigma sampling , ADE , IEEE , Variation , yield

Analog/Custom Design

Analog Design Resonance: Quick and Efficient Regression Scripts–Now Possible with…

The new Virtuoso ADE product suite is packaged with a lot of easy-to-use, productivity…

• 3 min read
ADE Explorer , ADE , Custom IC Design , ADE Assembler

Breakfast Bytes

CDNLive Boston Preview

The full agenda for CDNLive Boston is now available. This is really "East Coast"…

• 2 min read
CDNLive , Power Integrity , cdnlive boston , Boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

Nokia's Rise and Fall...and Maybe Rise Again

If you live in the US, then it is hard to believe how dominant Nokia was in mobile…

• 7 min read
microsoft , nokia , elop , mobile , Breakfast Bytes , iPhone

System, PCB, & Package Design 

What's Good About ADW’s Model Management? 16.6 Has a Few New Enhancements!

New Model Management capabilities are now available in the SPB 16.6 Allegro Design…

• less than a min read
Allegro 16.6 , flow manager , 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , setup , design data management , design , PCB design , Grzenia , model editor , library , ADW , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Smart Layer Behavior for Add Connect? It’s in…

When using the Add Connect command in the 16.6 Allegro PCB Editor , the active layer…

• less than a min read
PCB , Allegro 16.6 , layer stacks , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Two-Layer PCB Support? Check Out 16.6!

By default, the top and bottom stackup layers do not support the placement of embedded…

• 2 min read
Allegro 16.6 , layer stacks , via , PCB design , Grzenia , Allegro PCB Editor , Allegro
CDNS - Fix Layout Hompage