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Academic Network

Ultra-Wide-Band Workshop for Balkan Countries

Countries which were founded after the collapse of Yugoslavia have long tradition…

Anton Klotz 11 Oct 2016 • 1 min read

Croatia , Cadence Academic Network , academic workshop , Balkan , academia , Virtuoso , university program

Breakfast Bytes

RISC-V: the Case For and Against

At the Linley Processor conference recently, there was a presentation about RISC…

Paul McLellan 11 Oct 2016 • 7 min read

risc-v , linley processor conference , EEMBC , Linley , Krste Asanović , Breakfast Bytes , markus levy

Breakfast Bytes

DVCon Europe Preview

DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading…

Paul McLellan 10 Oct 2016 • 4 min read

Lanza , NXP , pswg , Perspec , iso26262 , DVcon , Accellera , DVCon Europe , ISO 26262 , portable stimulus , Breakfast Bytes

Verification

The Industry Vision for Portable Stimulus

As I mentioned in my last blog post , portable stimulus is one of the main areas…

tomacadence 7 Oct 2016 • 3 min read

uvm , pswg , Acceleration , Perspec , virtual platform , System Design and Verification , Emulation , System simulation and analysis , Accellera , FPGA prototypes , testbench , portable stimulus , silicon , verification

Breakfast Bytes

Cadence Implementation Flow for an ARM Cortex-A73 at 10nm

Increasingly, taking an appropriate ARM ® processor has become the standard way to…

Paul McLellan 7 Oct 2016 • 4 min read

cortex-a73 , TSMC , n10 , 10nm , ARM , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview October 10th to 14th (video)

https://youtu.be/Ej7aa83-OFM Monday: A preview of DVCon Europe on 19th/20th October…

Paul McLellan 6 Oct 2016 • less than a min read

Verification IP , risc-v , Memory , linley processor conference , MemCon , flash , linley group , VIP , MIPI , EEMBC , Arteris , mipi devcon , DRAM , cache-coherency , netspeed , DVcon , DDR , DVCon Europe , sddr , ARM , verification

Breakfast Bytes

Verific: the Name is Short for Verification...But That's Not What They Do

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific…

Paul McLellan 6 Oct 2016 • 4 min read

SystemVerilog , parser , IEEE 1801 , Verilog , verific , UPF , VHDL , Breakfast Bytes

Academic Network

Cadence Academic Network in Nordic countries

“Finland is not Scandinavia” was one of the first statements I heard, when I landed…

Anton Klotz 6 Oct 2016 • 4 min read

Finland , Cadence Academic Network , academia , KTH , Tampere , Norway , TUT , NTNU , Linkoeping , Sweden , university program

Breakfast Bytes

Tensilica Floating Point: Small, Similar Cycles and Lower Power

When I first started programming, the first programming language I learned was Fortran…

Paul McLellan 5 Oct 2016 • 6 min read

lx7 , DSP , fixed point , fortran , Linley , Tensilica , mathlab , floating point

Whiteboard Wednesdays

Whiteboard Wednesdays - How Much Floating Point Does Your Application Need?

To address the growing needs for floating-point arithmetic in DSP algorithms, all…

References4U 4 Oct 2016 • less than a min read

DSP , Whiteboard Wednesdays , IP , Tensilica , floating point

Analog/Custom Design

Virtuoso Video Diary: SPD – A Symbolic Way to Edit Your Physical Design

The best way to complete a complex task is to break it into smaller, simpler tasks…

Sucharita 4 Oct 2016 • 5 min read

symbolic placement of devices , SPD , Virtuoso Video Diary

Breakfast Bytes

1,168 Reasons to Watch Training Bytes

Well, they told me that starting blog titles with a number is good clickbait. The…

Paul McLellan 4 Oct 2016 • 2 min read

COS , self-learning , Cadence Online Support , training bytes

Verification

A Winning Strategy: Ethernet 10Base-T to Ethernet 400G!

Ethernet was developed in the 1970s and has been a viable communications protocol…

annkeffer 3 Oct 2016 • 2 min read

Verification IP , 802.3bs , 25G Ethernet , VIP , Ethernet standards , IEEE 802.3 , Ethernet , future of IP , CHI VIP , Ethernet 400G

Breakfast Bytes

5nm: Do You Take the Red Pill or the Blue Pill?

I wrote recently about the TSMC OIP Symposium where they talked about future devices…

Paul McLellan 3 Oct 2016 • 3 min read

tfet , 60 mV/decade , cnt , subthreshold sloope , carbon nanotube , Breakfast Bytes

Breakfast Bytes

How Can I Get Out of This House Without Going Anywhere Near Your Garage?

Go to any venture capitalist's website and they will have a bragging page with their…

Paul McLellan 30 Sep 2016 • 2 min read

anti-portfolio , ebay , starbucks , bessemer.google , OVP , venture capital

Verification

What is ISO 26262 and Why Should I Care?

ISO 26262 is a functional safety standard applied to the development of electrical…

RChilders 29 Sep 2016 • 3 min read

Automotive , functional safety , cadence , ISO 26262

Breakfast Bytes

Linley Gwennap: Specialization Spurs Processor Innovation

Every year in the fall, the Linley Group runs their processor conference. There are…

Paul McLellan 29 Sep 2016 • 5 min read

security , Intel , linley processor conference , AMD , x86 , IoT , Linley , ADAS , ARM , autonomous vehicles , power , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Why Is More Floating-Point Computation Required by DSP Applications…

Why is more floating-point computation required by DSP applications? More and more…

References4U 28 Sep 2016 • less than a min read

floating-point , DSP , Whiteboard Wednesdays , IP , communications processing , vision processing , Tensilica , wearables processing , floating point

Breakfast Bytes

What’s for Breakfast? Preview October 3rd to 7th (video)

https://youtu.be/dv54rKmMLRo Monday: Options for 5nm. Silicon can only cut…

Paul McLellan 28 Sep 2016 • less than a min read

60mV/decade , SystemVerilog , DSP , tensilica LX7 , CPF , Cadence videos , TSMC , parsers , Tensilica , training bytes , verific , n10 , 5nm , 10nm , ARM , floating point , VHDL , IEDM

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