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Memories Are Made of This: Preview of MemCon

This year's MemCon is on October 11, at the Santa Clara Convention Center. Last year…

Paul McLellan 28 Sep 2016 • 5 min read

vertical flash , Memory , LPDDR4 , MemCon , Micron , flash , NAND flash , Denali Party , DRAM , memcon 2016 , Breakfast Bytes

SoC and IP

3 Things You Didn't Know About MemCon 2016

Memcon is an event like few others, where SoC architects congregate to learn and…

Steve Brown 27 Sep 2016 • 1 min read

DDR4 , LPDDR4 , MemCon , DDR IP

Breakfast Bytes

TSMC: Technology Update

Twice a year TSMC has a big meeting in San Jose. These are the times that there is…

Paul McLellan 27 Sep 2016 • 7 min read

OIP , 3D packagin , HPC28 , CoWoS , IoT , 28nm , 20nm , 40ULP , fabless , TSMC , ULP , process roadmap , 55ULP , 16ff , 16nm , InFO , 16FFC , n7 , FinFET , n10 , 7nm , 10nm , foundry

System, PCB, & Package Design

Why Move Up to Allegro 17.2-2016? New Enhanced Backdrill Capability (Reason 4 of…

Adventures in Backdrilling For the past 15 years or so, routing high-speed interfaces…

mcatramb91 26 Sep 2016 • 4 min read

backdrill , Allegro 17.2 , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

System Design Enablement with Cadence and TSMC

System-on-chip (SoC) designers are always optimizing what has become known as PPA…

Paul McLellan 26 Sep 2016 • 3 min read

Low Power , bvp.system-ppa , virtual platform , TSMC , Tensilica , power , Breakfast Bytes

Verification

Back in the Saddle Again

Nearly five years ago, I signed off with my last blog post in the Cadence Community…

tomacadence 23 Sep 2016 • 3 min read

pswg , Perspec , System Design and Verification , System simulation and analysis , Accellera , portable stimulus , System Design and Verification , verification

Breakfast Bytes

Mellanox: Using Palladium ICA Mode

At CDNLive Israel, Yaron Netanel of Mellanox talked about his experience with Palladium…

Paul McLellan 23 Sep 2016 • 3 min read

Yaron Netanel , CDNLive , debug , mellanox , Palladium , in-circuit acceleration , ICA , cdnlive israel , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 26th to 30th (video)

https://youtu.be/1le_bd4o01Q Monday: System Design Enablement with Cadence and…

Paul McLellan 22 Sep 2016 • less than a min read

OIP , Memory , MemCon , LPDDR , liinley , SDE , TSMC , antiportfolio , DDR , system design enablement , bessemer ventures , power , microprocessor

Breakfast Bytes

How to Connect Sensors with I3C

A couple of sessions at MIPI DevCon last week were on I3C. This is a new generation…

Paul McLellan 22 Sep 2016 • 6 min read

MIPI , i2c , sensors , mobile , I3C

Analog/Custom Design

Virtuoso Video Diary: SKILL IDE Performance Analysis Tools

As a SKILL code developer, do you spend a major chunk of your time in fine-tuning…

deeptik 21 Sep 2016 • 2 min read

Team SKILL , programming , Virtuoso Video Diary , software development , SKILL IDE , Custom IC Design , SKILL++ , Virtuoso Layout Suite , SKILL

Breakfast Bytes

שלום from CDNLive Israel

Shalom. Today is CDNLive Israel in Tel Aviv. At least getting here from San Francisco…

Paul McLellan 21 Sep 2016 • 5 min read

CDNLive , Lip-Bu Tan , cdnlive israel , perlmutter

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of the PCIe Standard

In this week's Whiteboard Wednesdays video, Lana Chan explores the history of PCI…

References4U 20 Sep 2016 • less than a min read

Whiteboard Wednesdays , PCIe , PCI Express

Breakfast Bytes

MIPI: Not Just Mobile Any More

On September 14 and 15, MIPI held its first developer conference. For more background…

Paul McLellan 20 Sep 2016 • 3 min read

5G , Automotive , 4G , CSI-2 , Standards , MIPI , mipi devcon , ADAS , I3C , Breakfast Bytes

System, PCB, & Package Design

Why Move Up to Allegro 17.2-2016? New Padstack Editor – More Than Just a New GUI…

Customer inputs are key to product improvements I can read your minds as you…

edhickey 19 Sep 2016 • 5 min read

backdrill , Allegro 17.2 , keepouts , masks , padstack , PCB design , Why Move Up to 17.2 , Allegro

Breakfast Bytes

Signal and Power Integrity Masterclass

At CDNLive Boston, I moderated a panel session on signal and power integrity with…

Paul McLellan 19 Sep 2016 • 9 min read

DDR4 , CDNLive , dc-dc converters , IBM , Cisco , Oracle , cdnlive boston , advanced bus analysis , Qualcomm , compliance methodology

Academic Network

Cadence at the VLSI Design/CAD 2016 Symposium

Great Academic Networking in Taiwan With the support of the Cadence Academic Network…

Tracy Zhu 19 Sep 2016 • less than a min read

VLSI , Cadence Academic Network

Academic Network

ESSCIRC and ESSDERC in Lausanne

Since the year 2000, the European Solid-State Device Research Conference (ESSDERC…

ChristinaB 16 Sep 2016 • 2 min read

Cadence Academic Network , esscirc , essderc

Computational Fluid Dynamics

Masten Space Systems: Reuseable Space Craft Innovation With Cadence CFD Software

Until very recently, rockets that launched satellites into orbit were completely…

AnneMarie CFD 16 Sep 2016 • 5 min read

Breakfast Bytes

Are These Codecs Any Good? Netflix Tests Them

A codec compresses data for transmission. The first codec I had any close encounter…

Paul McLellan 16 Sep 2016 • 5 min read

GSM , audio codec , H.265 , codec , netflix , mobile , h.264 , video codec , Breakfast Bytes

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