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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Updates from the UVM Multi-Language (ML) Front

An updated version of the UMV-ML Open Architecture library is now available on the…

• 1 min read
funtional verification , SystemVerilog , UVM-ML , UVMWorld , UVM multi-language , e , SystemC

Analog/Custom Design

Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification

Key Findings : There are a host of issues that arise in mixed-signal verification…

• 5 min read
MS , uvm , Metric-Driven-Verification , Palladium , Mixed Signal Verification , Incisive , MDV-UVM-MS , Virtuoso , mixed signal , MDV

Whiteboard Wednesdays

Whiteboard Wednesdays—Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of…

• less than a min read
Whiteboard Wednesdays , IP , SoC , mobile , LTE

Verification

Code Coverage at the System Level with Hardware-Assisted Verification? Are You Kidding…

Short answer: Nope, not kidding. You can get value from applying code coverage with…

• 2 min read
hardware-assisted verification , code coverage , functional coverage , verification closure , verification

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Vertically Placed Components? It’s in the 16…

The ‘dual_sided_component’ property in the Allegro PCB Editor 16.6 release can be…

• 1 min read
embedded components , interconnects , Allegro 16.6 , PCB design , Allegro PCB Editor

Verification

Dealing with Specman-Simulator Interface Issues—Get Ready to Cook!

Two great documents, aiming to make life easier for a verification engineer, were…

• less than a min read
Specman , debug , Functional Verification , Incisive , e language , simulation

Verification

Time to Play - You Can Now Run Your e Code on EDAplayground

Over the years I've often hoped to have the ability to show someone (a customer,…

• less than a min read
IEEE 1647 , Functional Verification , tech tips , EDA , e language , team specman , Aspect Oriented Programming

SoC and IP

USB Power Delivery Is Better with Type-C

In my previous blog post , I wrote how much better than the existing Type-A and Type…

• 2 min read
USB 3.0 , Design IP , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Verification

Code Coverage at the System Level with Hardware-Assisted Verification (Part II)

In yesterday’s Part I blog post , I talked about a technique for focusing code coverage…

• 4 min read
hardware-assisted verification , code coverage , system-level code coverage , coverage analysis , functional coverage

Analog/Custom Design

Five Reasons I'm Excited About Mixed-Signal Verification in 2015

Key Findings : Many more design teams will be reaching the mixed-signal methodology…

• 7 min read
uvm , mixed signal design , Metric-Driven-Verification , Mixed Signal Verification , MDV-UVM-MS

Whiteboard Wednesdays

Whiteboard Wednesdays—Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends…

• less than a min read
Whiteboard Wednesdays , DDR4 , DRAM , DDR3

Whiteboard Wednesdays

Whiteboard Wednesdays—Selecting the Right DDR PHY Solution

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation…

• less than a min read
Whiteboard Wednesdays , IP , Floorplanning , PHY IP , DFI

Analog/Custom Design

Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip Simulations…

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test…

• 9 min read
Advantest , Palladium , Mixed Signal Verification , Emulation , mixed signal

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Select by Lasso or Path? 16.6 Has It!

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , cadence , Routing , route quality , bulk editing , SPB , PCB Editor , PCB design , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , TripleCheck

System, PCB, & Package Design 

Multi-Fabric Planning for Efficient PCB Design

Recently, an article was published in Printed Circuit Design and Fab about Multi…

• 1 min read
BGA-style package , PCB design , multi-fabric planning , pin assignment

Analog/Custom Design

Virtuosity: A Very Large Number of Things I Learned in September and October 2014…

There has been a flurry of activity on COS over that past couple of months. I can…

• 8 min read
AMS , MMSIM , Advanced Node , ADE XL , Virtuoso , Analog Design Environment , Custom IC Design , Virtuoso Layout Suite XL , IC 6.1.6

Verification

Where Is the Money for IoT?

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which…

• 1 min read
Verification IP , DSP , IP , IoT , Tensilica , always-on

System, PCB, & Package Design 

Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP Layout Makes Your…

As these types of designs see an increasing number of applications and design starts…

• 4 min read
IC Package , SiP Design , Co-Design , layout pin numbering
CDNS - Fix Layout Hompage