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Verification

UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented…

teamspecman 23 Nov 2012 • 1 min read

AF , uvm , Specman , Functional Verification , vr_ad , Register Package , e language , UVMe , register enhancements

RF Engineering

MMSIM 12.1 SpectreRF -- Preview of Coming nport Attractions! Part 2

Greetings, MMSIM 12.1 contains many new features to aid RF designers. Many of these…

Tawna 19 Nov 2012 • 2 min read

nport , RF , RF Simulation , analog/RF , Circuit simulation , Wilsey , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , ADE-L , Analog Simulation , MMSIM , nport settings , Virtuoso Spectre Simulator GXL , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , harmonic balance , simulation

Verification

Optimizing ARM Based Designs for Low Power using Emulation

The month November goes to the Brits, no question. Not only did the James Bond movie…

fschirrmeister 19 Nov 2012 • 5 min read

ESL Market , Nufront , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Peng Wang , cadence , Acceleration , Functional Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Palladium XP , Emulation , ARM , Schirrmeister , low power optimization

Verification

Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are…

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying…

teamspecman 16 Nov 2012 • less than a min read

IEEE 1647 , Specman , Hannes Froehlich , Functional Verification , MOOC , Udacity , training , VA Partners , verification alliance , e language

Digital Design

The Case for the Tiny Testcase

I often joke with customers that, although I realize they have to work on large designs…

BobD 16 Nov 2012 • 2 min read

debug , tiny testcase , testcase , Test , encounter , Digital Implementation , small testcase , test case , Bob Dwyer , verification

Analog/Custom Design

Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes

Are you working in the area of mixed signal? Then you may want to exchange information…

AndreasLenz 15 Nov 2012 • 1 min read

ITDB , mixed-signal training , Andreas Lenz , analog on top , CPF , Mixed-Signal , encounter , Virtuoso , mixed signal , mixed-signal forum , OpenAccess , forum , Cadence Community

Analog/Custom Design

Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical…

The recently concluded ARM TechCon 2012 , the annual event for ARM users (including…

Sathish Bala 14 Nov 2012 • 2 min read

ARM Techcon , EDI , chipestimate , ARM Cortex M0 , AMS Designer , ARM Technology Symposium , 20nm , 14nm , Mixed-Signal , Virtuoso , mixed-signal book , Cortex-M0 , mixed signal , mixed-signal design , ARM , ARM-Cortex-M

Verification

CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available…

Jack Erickson 14 Nov 2012 • 1 min read

High-Level Synthesis , video processor , Jack Erickson , CDNLive , System Design and Verification , Freescale , rtl compiler , C-to-Silicon , Israel , SystemC , CDNLive! , DAC 2012 , HLS , ESL

System, PCB, & Package Design

What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!

In some designsflows, you need to connect two plane shapes on the same net, but on…

Jerry GenPart 13 Nov 2012 • 5 min read

PCB , IC Packaging and SiP Design , blind vias , IC Packaging , Allegro GUI , inset vias , Allegro 16.6 , packaging , Digital SiP design , layer stacks , High Speed , shape shorting , APD , IC/package co-design , Allegro Package Designer , advanced package designer , via , design , vias , PCB design , Grzenia , shorting vias

RF Engineering

MMSIM12.1 SpectreRF Preview of Coming Attractions! - Part 1

Greetings! MMSIM 12.1 contains many new features to aid RF designers. Here's a preview…

Tawna 12 Nov 2012 • 2 min read

RF , RF Simulation , analog/RF , envelope , Circuit simulation , Wilsey , shooting newton , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , ADE-L , Analog Simulation , MMSIM , fast envelope , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , RF design , harmonic balance

Digital Design

Transitioning Your LEF-Based EDI System Design Flow to OpenAccess

The trend of combining analog and digital circuits on a single chip has been growing…

wally1 12 Nov 2012 • 4 min read

EDI system , LEF , Cadence Online Support , Mixed-Signal , encounter , Virtuoso , oa , Digital Implementation , PDK , mixed signal , LEF to OpenAccess , Brian Wallace , OpenAccess , blog

Verification

Function Level C Interface – New C Interface for Specman

Working with the conventional Specman C language interface has two major disadvantages…

teamspecman 6 Nov 2012 • 2 min read

AF , Specman , function level , Functional Verification , C Interface , e language , Specman C , TCM , PLI

System, PCB, & Package Design

What's Good About Allegro PCB Editor Component Alignment? See for Yourself in 16

The Component Alignment feature is available in Placement Edit Application mode.…

Jerry GenPart 5 Nov 2012 • 1 min read

PCB , DFA , Allegro 16.6 , 16.6 , Placement Edit , Component Alignment , PCB Editor , PCB design , Grzenia , Spacing , Allegro PCB Editor , alignment , Allegro

Verification

Creating Custom File Systems and the Linux Loop Device

A few weeks ago we had a crisis at our house. My son managed to delete the data from…

jasona 5 Nov 2012 • 7 min read

virtual platforms , Linux loop , File System , virtual prototypes , chroot , System Design and Verification , embedded software , Ubuntu , linaro , custom file systems , mount -o loop , ARM Architecture , Zynq virtual platform , linux , Jason Andrews , Zynq-7000 , simulation

Verification

How Many Cycles are Needed to Verify ARM’s big.LITTLE on Palladium XP?

At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar…

fschirrmeister 30 Oct 2012 • 5 min read

ESL Market , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , Functional Verification , System Design and Verification , big.LITTLE , System Development Suite , embedded software , Palladium XP , Emulation , ARM , cost of ownership

System, PCB, & Package Design

What's Good About the SPB 16.6 Release? Exciting Features To Improve Design Productivity

The SPB 16.6 Release is available! You can download it from the Cadence Software…

Jerry GenPart 30 Oct 2012 • 4 min read

Analog/Custom Design

Recent Events Show That Customer Interest in Mixed-Signal Remains High

The well attended Mixed-Signal Technology Summit last month really demonstrated the…

QiWang 30 Oct 2012 • 2 min read

ARM Techcon , ARM Cortex M0 , mixed signal design , Technology on tour , MS ToT , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , Open Access , Cortex-M , Mixed-Signal , Mixed-Signal Technology Summit , analog/mixed-signal , mixed-signal book , Cortex-M0 , Mixed-Signal Tech Summit , mixed signal methodology guide , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , ARM , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess , AMS Verification

Verification

Event Report: Club Formal San Jose – Features and Techniques for Experts, Verification…

Last week over 35 power users from over a dozen companies came together for the latest…

TeamVerify 25 Oct 2012 • 5 min read

Incisive Formal Verifier , ABV , Team Verify , Functional Verification , Formal Analysis , formal apps , Vigyan Singhal , Incisive , Incisive Enterprise Verifier , Chelsio , Chris Komar , apps , assertions , Club Formal , bypass logic verification , IEV , Oski , Formal verification , IFV , liveness , Assertion-based verification

Verification

Ubuntu 12.10 on a Virtual Platform at ARM Techcon

Next week (Oct. 30-Nov. 1) ARM TechCon 2012 is at the Santa Clara Convention Center…

jasona 25 Oct 2012 • 1 min read

ARM Techcon , Virtual System Platform , virtual platforms , programmer's guide , virtual prototypes , Cortex-A9 , Cortex-A , VSP , Ubuntu , ARM , Quantal Quetzal , Ubuntu 12.10 , linux , Jason Andrews , Zynq-7000

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