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What's Good About Allegro PCB Editor GUI updates? See for Yourself in 16.5!

The 16.5 Allegro PCB Editor release contains several updates to the Graphical User…

Jerry GenPart 7 Aug 2012 • 2 min read

PCB , PCB Layout and routing , Allegro GUI , status bar , super filter , Allegro 16.5 , PCB Editor , PCB design , 16.5 , Allegro PCB Editor , etch class , Allegro

SoC and IP

Cadence Video Demonstrates PCIe Gen3 IP Silicon Performance

It is not often that an IP provider gets to showcase their IP performance in a real…

ashwinmatta 6 Aug 2012 • 1 min read

controller IP , Design IP , IP , PCI Express 3.0 , Gen3 , video , Matta , storage , SAS RAID , PCIe , PCIe Gen3 , PCI Express Gen3 , PCI Express

Verification

SimVision Watch Window Now Accommodates Specman Watch Items

Starting from version 12.1, the SimVision Watch Window accommodates Specman watch…

teamspecman 6 Aug 2012 • less than a min read

AF , Specman , gui , watch window , debug , Functional Verification , specview , Specman watch , simvision , SimVision watch window , watches , Chudnovsky

Digital Design

In Case You Missed It – The Most Popular EDI System Knowledge Content Published in…

I mentioned in my first blog one of my roles in customer support is to identify and…

wally1 6 Aug 2012 • 2 min read

EDI , AOCV , advanced on-chip variation , Cadence Online Support , encounter , OCV , Digital Implementation , Encounter Digital Implemention , app notes

Digital Design

How To: Bring Up Encounter "man" Pages from a UNIX Prompt

Okay, this one is too cool not to share. The other day a customer and I were trying…

BobD 1 Aug 2012 • 1 min read

documentation , Unix prompt , EDI , man pages , encounter digital implementation system , Tips , help , Digital Implementation , man , tricks

Verification

Video: Interview with Professional Teenage Technology Coach Kristine Bonhoff

Over the past several years at various EDA trade events, one of the more popular…

jvh3 31 Jul 2012 • 1 min read

Joe Hupcey III , Kristine Bonhoff , interview , video , EDA360 , apps , teen tech

Verification

Product Update: New Assertion-Based Verification IP (ABVIP) Available Now

Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP…

TeamVerify 30 Jul 2012 • 2 min read

Incisive Formal Verifier , Jose Barandiaran , ABV , Functional Verification , ABVIP , formal , formal apps , assertions , IEV , Incisive Enterprise Simulator (IES) , Formal verification , IFV , verification , Assertion-based verification , IES-XL

Digital Design

10 Encounter Tips and Tricks You May Not Be Aware Of

In looking over the shoulders of Encounter users over the years I've found there…

BobD 27 Jul 2012 • 1 min read

EDI , Routing , power routing , encounter digital implementation system , IC layout , NanoRoute , Tips , encounter , tips and tricks , Digital Implementation , signal routes , log file , tricks , tcl

Verification

Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal…

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through…

jvh3 24 Jul 2012 • 1 min read

digital mixed-signal , AMS , uvm , Joe Hupcey III , verification strategy , Verification methodology , Functional Verification , UVM-MS , Neyaz Khan , Mixed Signal Verification , Mixed-Signal , DVcon , Maxim Semiconductor , verification

Verification

My Constraint was Ignored – Is it a Tool Bug? – Part 2

In a previous post we showed some cases of user code that can cause ignored constraints…

teamspecman 23 Jul 2012 • 3 min read

AF , IntelliGen , Specman , debug , Functional Verification , Generation , e language

Digital Design

Capturing and Processing Encounter Console Output with "redirect"

In my last post I wrote about writing more compact db access scripts with dbGet's…

BobD 23 Jul 2012 • 4 min read

dbGet , EDI , write nets to file , Console output , encounter , redirect , Encounter Digital Implementation , Dwyer , tcl

System, PCB, & Package Design

What's Good About Customer Support AppNotes? They Will Increase Your Productivity

Our Silicon Package Board (SPB) Customer Support team has initiated a new blog series…

Jerry GenPart 17 Jul 2012 • less than a min read

PCB , PCB Layout and routing , customer support , applications , Allegro 16.5 , Appnotes , PCB Editor , Allegro performance , Layout , design , PCB design , 16.5 , SPB16.5 , Allegro PCB Editor , application note , OrCAD PCB Editor , Online Support , Allegro

Verification

UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition…

teamspecman 16 Jul 2012 • 1 min read

AF , uvm , Specman , methodology , Testflow , Functional Verification , testflow phase debugging , testflow phases , advanced verification , e language , blocking activities , IES-XL

System, PCB, & Package Design

Customer Support Recommended - Appnote on Increasing Performance in Allegro PCB …

While working on very large scale Printed Circuit Board (PCB) files that contain…

Naveen 16 Jul 2012 • 1 min read

COS , PCB , PCB Layout and routing , customer support , Performance Advisor , Support , Allegro 16.5 , PCB Editor , Allegro performance , Layout , Appnote , dbdoctor , PCB design , SPB16.5 , Allegro PCB Editor , application note , Online Support , Allegro

Analog/Custom Design

Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4…

QiWang 10 Jul 2012 • 3 min read

mixed-signal seminars , Beijing , AMS , China , mixed signal design , Technology on tour , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , analog , Mixed-Signal , Shenzhen , mixed signal methodology guide , mixed signal , ARM , tech-on-tour , Shanghai , AMS Verification , mixed-signal verification

Digital Design

Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation…

As you know, Cadence Online Support is your 24/7 site for getting help and resolving…

wally1 9 Jul 2012 • 2 min read

SoC-Encounter , Cadence On-Line Support , Low Power , Foundation Flow , DBTcl , EDI system , Signoff Analysis , Low-Power , EDI 11.1 , Cadence Online Support , NanoRoute , Silicon Realization , Digital Implementation , EDI system Encounter Digital Implementation System , CTS , Enouter Timing System , Rapid Adoption Kits , RAKs , SoC-Encounter dbGet dbSet

Verification

Using Flexible Specman License Searches

Until recently, Specman used to look for its licenses in the following strict, hardcoded…

teamspecman 9 Jul 2012 • 2 min read

AF , Specman , new features , Functional Verification , licenses , license search , Incisive , e language , Specman licenses , verification , IES-XL

Verification

Adding Xilinx C Models to the Virtual Platform of the Zynq-7000 EPP

Today, I have a good article from Henry Von Bank of Posedge Software related to Zynq…

jasona 9 Jul 2012 • 5 min read

Virtual System Platform , zynq , virtual platforms , TLM , posedge , IP-XACT , Henry Von Bank , virtual prototypes , VSP , RDF , SystemC , xilinx , ARM , FFT , Zynq virtual platform , Zynq-7000

System, PCB, & Package Design

What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

This week, I'm providing a very short blog. While the content is brief and simple…

Jerry GenPart 6 Jul 2012 • less than a min read

capture , "capture CIS" , OrCAD Capture Marketplace , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , design , OrCAD , Design Entry , SPB16.5 , PCB Capture , Schematic

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