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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Digital Design

Five-Minute Tutorial: Default Naming Conventions in Encounter Digital Implementation…

This is a topic that frequently comes up on both internal and external forums. And…

• 2 min read
EDI , naming , timing debug , tutorial , encounter , Digital Implementation , Encounter Digital Implementation , default naming conventions , five-minute

System, PCB, & Package Design 

Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB S…

Altera and Cadence recently collaborated and completed correlation work with Allegro…

• 2 min read
PCB SI , PCB , Stratix V , Multi-Gigabit , Altera , IBIS , model kit , PCB power integrity , FPGAs , IBIS-AMI , Signal Integrity , PCB design , channel analysis , SI analysis and modeling , FPGA , Allegro

Verification

Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17th North American SystemC User Group meeting ( NASCUG ), will take place this…

• 3 min read
IP , zynq , virtual platforms , TLM , platform , virtual prototypes , fixed sub-systems , sub-systems , Tensilica , subsystems , OMAP , DVcon , SystemC , xilinx , NASCUG , FPGA , System Design and Verification , verification

Verification

Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has…

• less than a min read
performance , SystemVerilog , Multi-Core , Incisive , Funcional Verification , Incisive Enterprise Simulator (IES) , IES , IES-XL

System, PCB, & Package Design 

What’s Good about OrCAD Apps? Symbol and Footprint Creation Just Got a Lot Easier…

Creating the symbols and footprints necessary to complete your designs can be a difficult…

• 2 min read
PCB , Marketplace , OrCAD Capture Marketplace , Footprint , OrCAD Capture , Capture CIS , Capture-CIS , OrCAD online store , Library flow , Allegro 16.5 , Library and design data management , SPB , webinar , symbol , OrCADapps , "PCB design" , OrCAD , PCB design , Design Entry , SPB16.5 , Librarians , library , PCB Capture , Schematic , Allegro

System, PCB, & Package Design 

What's Good About Capture’s Placement Report? Look to SPB16.5 and See!

The 16.5 release of OrCAD Capture includes the ability to generate a report with…

• less than a min read
"capture CIS" , Allegro Design Entry , hierarchy , Design Entry CIS , flat schematics , Capture CIS , Capture-CIS , property , hierarchical schematics , Allegro 16.5 , SPB , placement report , design , OrCAD , 16.5 , Design Entry , SPB16.5 , PCB Capture , Schematic , Allegro

Verification

Using a Linaro File System on the Cadence Virtual Platform for the Xilinx Zynq-7000…

Linaro has emerged as a great place to find well tested toolchains, Linux kernels…

• 3 min read

Verification

DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

In a few short weeks DVCon 2012 will be upon us ( Feb. 27 - March 1 in San Jose …

• 2 min read
Joe Hupcey III , ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , Bin Ju , video , tutorial , Facebook , Chris Komar , DVcon , apps , assertion synthesis , assertions , robot , IEV , Assertion-Driven Simulation , Darrow Chu , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About ADW’s Server Metrics? Check out the 16.5 Release and See!

The Allegro Design Workbench (ADW) 16.5 has the capability of providing usage metrics…

• 1 min read
PCB , data management , usage metrics , Allegro Design Workbench , Library flow , server metrics , Team design , Allegro 16.5 , SPB , LRM , design data management , configuration manager , design , Library Revision Manager , PCB design , SPB16.5 , metrics , library , ADW

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 5

In the previous SKILL for the Skilled postings, we looked at a pretty good algorithm…

• 4 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Measurements Across Corners

In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested…

• 1 min read
Corners , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Corners analysis , IC615 , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design

Digital Design

Five-Minute Tutorial: Change The Background Color Of EDI

Today's tutorial could probably be called a One-Minute Tutorial, since it's so quick…

• 1 min read
EDI , changing color , color , encounter , Digital Implementation , five minute tutorial , background color

Verification

The Zynq Virtual Platform: Not Just for Pre-Silicon

One of the biggest misconceptions about Virtual Platforms is that they are only useful…

• 4 min read
Virtual System Platform , zynq , virtual platforms , Zynq-7000' , pre-silicon , virtual prototypes , post-silicon , embedded software , Watchdog Timer , SystemC , linux

System, PCB, & Package Design 

What's Good About Property Changes in DEHDL? The Secret's in the 16.5 Release!

In the 16.5 release, all connectivity changes are stored in the hierarchical block…

• 11 min read
PCB , Allegro Design Entry , hierarchy , electrical constraints , flat schematics , uprev , hierarchical schematics , property changes , Allegro 16.5 , Constraint Manager , Design Entry HDL , design , Design Entry , SPB16.5 , ConceptHDL , Schematic , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Signal Integrity Application Mode? It’s in the 16.5 Release

In release 16.0, the concept of Application Modes was introduced. These application…

• 2 min read
PCB SI , PCB , PCB Layout and routing , SI , application mode , High Speed , Allegro 16.5 , Layout , Signal Integrity , PCB Signal integrity , PCB design , 16.5 , Allegro

Verification

System-Level Design and the Waves of EDA

Before January comes to an end it is time for my annual flashback and brief reflection…

• 5 min read
virtual prototypes , IP integration , abstraction , VCC , VSI , IP assembly , cars , EDAC , software , automobiles , 1997 , Virtual Platforms , IEEE Spectrum , Schirrmeister , ESL , ESL system-level design

Verification

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level…

• 2 min read
verification speed , whitepaper , uvm , Low Power , gate level , simulation speed , Functional Verification , Incisive Enterprise Simulator , 20nm , Low-Power , Incisive , Mixed-Signal , gate-level , Incisive performance , Simulation acceleration , DVcon , testbench , Incisive Enterprise Simulator (IES) , simulation , IES , Assertion-based verification , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: We've Got You Cornered

One of the big buzzwords around the EDA world these days is "variation." Don't you…

• 3 min read
Corners , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design , corner analysis

Verification

Video Killed the Reference Manual Star

[Preface: recall the melody of the Buggles' 1979 hit " Video Killed the Radio Star…

• 1 min read
ABV , videos , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , YouTube , SVA , PSL , assertions , Axel Scherer , MDV , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification
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