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Verification

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Earlier this year, Cadence announced the expansion of its VIP Catalog to include…

PeteHeller 14 Sep 2012 • 2 min read

validation. , Driver , firmware , System Design & Verification

Verification

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study…

Right up there with functional verification, the challenges of low power design and…

jvh3 12 Sep 2012 • 3 min read

uvm , Low Power , GoPro Hero2 , thermal verification , Functional Verification , MCAD , video , mechanical design automation , EDA , low-power design , thermal behavior , heat dissipation

System, PCB, & Package Design

What's Good About ADW’s Flow Manager? Check out the 16.5 Release and See!

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

Jerry GenPart 11 Sep 2012 • 1 min read

PCB , data management , symbol editor , flow manager , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , Library and design data management , SPB , Design Entry HDL , design data management , symbol , design , PCB design , Design Entry , Grzenia , SPB16.5 , Librarians , library , ADW , Schematic , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 2, Many Ways to Sum a List

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1 …

Team SKILL 10 Sep 2012 • 4 min read

Team SKILL , Jim Newton , sum a list , summing , Virtuoso , software development , SKILL++ , SKILL

Digital Design

Simple Steps to Debug DRC Violations Undetected in EDI System

You've placed and routed your design in the Encounter Digital Implementation (EDI…

wally1 10 Sep 2012 • 4 min read

EDI , DRC , design rules , DRC signoff , LEF , Cadence Online Support , NanoRoute , encounter , Digital Implementation , Encounter Digital Implementation , Verify Geometry , PVS , DRC violations , debug DRC violations

Analog/Custom Design

Things You Didn't Know About Virtuoso: The (Setup) State of Things

Apologies for the long delay between articles (best intentions and all that). I last…

stacyw 5 Sep 2012 • 3 min read

Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , setup states , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Custom IC Design

Analog/Custom Design

SKILL for the Skilled: Part 1, Many Ways to Sum a List

A while back I presented a one day SKILL++ seminar to a group of beginner and advanced…

Team SKILL 5 Sep 2012 • 3 min read

Jim Newton , sum a list , summing , Virtuoso , apply , software development , SKILL++ , sumlist , SKILL

Verification

UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation…

teamspecman 5 Sep 2012 • 2 min read

AF , uvm , Specman , BFM , Testflow , Functional Verification , testflow phases , e language , team specman , sequences , Reset mechanism , Shneydor , verification , sequence driver

Verification

What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else…

teamspecman 5 Sep 2012 • 3 min read

IEEE 1647 , SystemVerilog , scoreboard , uvm , Specman , Specman/e , UVM e , vr_ad , UVM-e , advanced verification , e language , UVC , SCE-MI , team specman , Constraints , Aspect Oriented Programming , sequences , Incisive Enterprise Simulator (IES) , Shneydor , AOP

System, PCB, & Package Design

What's Good About DEHDL’s Find Functionality? The Secret's in the 16.5 Release!

The current Allegro Design Entry HDL (DEHDL) Page Search toolbar works only on the…

Jerry GenPart 4 Sep 2012 • 3 min read

DEHDL find , page search , hierarchy , flat schematics , super filter , selection filters , property changes , Allegro 16.5 , Design Entry HDL , Find result , design , Design Entry , Grzenia , highlighting , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

Verification

Introduction to the Linux Kernel Message System

One of the most common problem reports related to Virtual Platforms running Linux…

jasona 4 Sep 2012 • 6 min read

Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , System Design and Verification , kernel messaging system , Andrews

System, PCB, & Package Design

What's Good About PCB SI Adaptive Mesh Generation? 16.5 Has Many New Enhancements

The 16.5 PCB SI product’s rectangular mesh scheme is used for shapes, cutouts, slots…

Jerry GenPart 28 Aug 2012 • 2 min read

PCB SI , PCB , SI , PI , PCB PI , PDN , Signal Intregrity , SI bus analysis , SigXP UI , PCB Signal and power integrity , "PCB SI" , High Speed , Allegro 16.5 , SPB , High-Density Interconnect , full wave , Signal Integrity , full-wave , PDN Analysis , OrCAD PCB SI , field solver , Allegro PCB SI , PCB design , "PCB PI" , adaptive mesh generation , Grzenia , SPB16.5 , SI analysis and modeling , Meshing , HDI , Allegro

Analog/Custom Design

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference…

Sathish Bala 27 Aug 2012 • 3 min read

real number modeling , DAC , uvm , IP , A/MS , Verilog-AMS , analog , co-simulation , Mixed-Signal , analog behavioral models , analog/mixed-signal , model validation , RNM , metric-driven verification , VHDL-AMS , assertions , mixed signal , mixed-signal design , wreal , real number models , Design Automation Conference , SPICE , mixed-signal verification , verification , stmicroelectronics , real number

System, PCB, & Package Design

Customer Support Recommended – Appnote on Implementing the Force-Sense Kelvin Co…

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin…

Naveen 23 Aug 2012 • 2 min read

PCB , Kelvin connection , Allegro Design Entry , customer support , part developer , DEHDL , PDV Symbol , Allegro 16.5 , Appnotes , PCB Editor , Design Entry HDL , Appnote , symbol , Force-Sense , PCB design , 16.5 , force sense , SPB16.5 , ConceptHDL , application note , Schematic , Allegro , Kelvin

System, PCB, & Package Design

What's Good About APD’s Wire Bond Settings Groups? You’ll Need the 16.5 Release to…

The 16.5 Allegro Package Design (APD) product has been modified to provide a different…

Jerry GenPart 21 Aug 2012 • 4 min read

PCB , PCB Layout and routing , packaging , APD , Allegro 16.5 , Wirebond , Allegro Package Designer , wire bond settings groups , PCB design , Grzenia , wire bond , Allegro

Verification

Report From Silicon Valley With Application Engineer Bin Ju

Luckily I was able to track down my very busy colleague Bin Ju between assignments…

TeamVerify 21 Aug 2012 • less than a min read

Joe Hupcey III , ABV , Formal Analysis , Bin Ju , formal , video , formal apps

Verification

Improving SimVision Fonts for Ubuntu

This article is a follow-up on an early 2012 article about using Incisive and Virtual…

jasona 17 Aug 2012 • 4 min read

Virtual System Platform , virtual platforms , System Design and Verification , VSP , Incisive , Ubuntu , Ubuntu 12.04 , SystemC

Verification

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape…

teamspecman 15 Aug 2012 • 6 min read

Specman , Specman/e , debug , simvision , Incisive , SimCompare , e language , chip-level debugging , Funcional Verification , reflection , irun , testbench , simulation

System, PCB, & Package Design

What's Good About Allegro PCB Router Routing Changes? 16.5 Has a Few New Enhancements

The 16.5 Allegro PCB Router has a couple new improvements I’ll cover today – Embedded…

Jerry GenPart 15 Aug 2012 • 2 min read

PCB , PCB Layout and routing , embedded components , Routing , route quality , Allegro 16.5 , diff pair , PCB Editor , differential pair , Allegro router , PCB design , Grzenia , Allegro

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