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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

UVM - The Progress Continues With Reference Flow

As 2010 ends and 2011 begins, the most important thing that came out of the Universal…

• 1 min read
uvm , Functional Verification , EDA360 , Coverage-Driven Verification , EDA , AMIQ , verification

Analog/Custom Design

On-Demand Webinar: Parasitic-Aware Design Part1 -- A Complete Analog Design Flow

If you were not able to attend this recent live webinar, or were able to and would…

• less than a min read
analog , Virtuoso , Custom IC Design , parasitics

Verification

A Look Back at ARM Techcon 2010: Surprising Keynotes, New Products, and Lego!

The acid test of any conference is how long after the keynotes, panels, and demos…

• 4 min read
A-15 , Industry Insights , Cortex , GPU , IBM , Mali , EDA360 , linaro , blogs , ecosystem , moore's law , EUV litho , Marvell , ARM , Techcon

Verification

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

2010 was a very dynamic year for the electronic systems industry overall, and for…

• 5 min read
High-Level Synthesis , TLM2 , ASIC , TLM-driven design , CDNLive , cadence , Acceleration , C to Silicon , system realization , System Design and Verification , C-to-Silcon , EDA360 , ASIC/ASSP , rtl compiler , Co-verification , metric-driven verification , C-to-Silicon Compiler , Virtual Platforms , Synthesis , high level synthesis , ARM , MDV , ESL , System Design and Verification

Verification

Those Corner-Case Conditions Caught You Again!

In my last blog post , I related a story from my engineering past in which I learned…

• 3 min read
sjc , Functional Verification , bugs , corner cases , airport

System, PCB, & Package Design 

What's Good About Allegro Widths & Gaps & Diff Pairs? Oh My – Check Out SPB16.3!

The SPB16.3 release of Allegro PCB Editor now provides the ability to resize line…

• 2 min read
PCB Layout and routing , SPB16.3 , diff pairs , gaps , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , design , "PCB design" , PCB design , widths , Allegro PCB Editor , differential pairs , Differential Pair Support , Allegro

Verification

How Do You Debug Your Testbench when it Won’t Stand Still?

The task of debugging a simulation problem in your design can be a difficult and…

• 1 min read
whitepaper , uvm , debug , Functional Verification , bugs , simvision , OVM , Incisive , testbench

Verification

On-Demand Webinar: TLM Design and High-Level Synthesis

In case you missed it last week, Mark Warren delivered a very informative webinar…

• less than a min read
TLM , C to Silicon , webinars , RTL , System C , SystemC , System Design and Verification

Analog/Custom Design

Making Friends With Parasitic Effects

OK, so the title is perhaps a little optimistic but I'm playing off the saying …

• 2 min read
PAD , Bleasdale , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , Parasitic analysis , Custom IC Design , parasitics

Verification

Corner-Case Conditions Will Get You Every Time

Experienced verification engineers know that most killer bugs lurk deep in the corners…

• 2 min read
Functional Verification , bugs , corner cases , dec , Gordon Bell

Verification

New Interview with Partner Zocalo on Their Assertion Creation Philosophy and Approach…

Heads-up Team Verify subscribers: on his "Industry Insights" blog Richard Goering…

• less than a min read
DAC , ABV , Zocalo , verification strategy , Verification methodology , Functional Verification , formal , assertions , verification

Verification

A SystemC TLM 2.0 ARM Linux Boot Loader

Earlier this year I wrote an article with some details related to loading Linux into…

• 6 min read
TLM2 , virtual platforms , System Design and Verification , TLM 2.0 , embedded software , boot loader , software , SystemC , ARM , linux , System Design and Verification , kernel

System, PCB, & Package Design 

What's Good About Capture Intersheet References? The Secret's in the SPB16.3 Release

The SPB16.3 release of OrCAD Capture now allows you to create intersheet references…

• 5 min read
PCB , SPB16.3 , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , OrCAD , intersheet , Design Entry , Schematic , Allegro

RF Engineering

Measuring Transistor fmax

There were several questions about measuring transistor f max in comments posted…

• 3 min read

Analog/Custom Design

SKILL for the Skilled: Rule of English Translation

An obvious criticism of my previous post SKILL for the Skilled: Making Programs…

• 3 min read
Team SKILL , English translation , Norvig , Lisp , Custom IC Design , SKILL , clarity

Verification

“Everything Assertion Based” -- Assertion-Based Verification (ABV) Comes of Age for…

Preface: are you having trouble (re-)igniting interest in formal, muti-engine, and…

• 5 min read
NextOp , ABV , Zocalo , Functional Verification , Formal Analysis , formal , VIP , PSL , assertion synthesis , metric-driven verification , coverage driven verification (CDV) , assertions , AMBA , MDV , IEV , IFV

System, PCB, & Package Design 

What's Good About Mechanical Parts in ADW? Check Out the ADW16.3 Release and See

Mechanical part support! It's here in the Allegro Design Workbench (ADW16.3) release…

• 2 min read
PCB , SPB16.3 , DEHDL , mechanical parts , SPB 16.3 , Library flow , Library and design data management , PCB Editor , Design Entry HDL , Front-end PCB design , design , Component Information Portal (CIP) , Design Entry , ADW 16.3 , Allegro PCB Editor , ConceptHDL , library , ADW , Allegro

SoC and IP

The 3D SSD

You need three things from a solid-state disk (SSD): speed, capacity, and reliability…

• 1 min read

Verification

Evolution and Synthesis

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over…

• 2 min read
High-Level Synthesis , RTL , Hogan , EETimes , SystemC , evolution , HLS , McLellan
CDNS - Fix Layout Hompage