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Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI

Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Performance Tips and Tricks: Coding e Ports for Enhanced Performance

This blog entry builds on last week's Tips and Tricks posting in which we discussed…

• 3 min read
IntelliGen , Specman , vr_ad , OVM-e , Funcional Verification , team specman , AOP , IES-XL

SoC and IP

The 6-minute video guide to memristors (must-see video)

With the August 31 announcement that Hynix is now working with HP to bring the semi…

• less than a min read

SoC and IP

Chemical vapor deposition creates improved material for PCM (phase-change memory…

Yesterday, semiconductor materials manufacturing specialist ATMI and Ovonics, the…

• less than a min read

SoC and IP

Commodore and its iconic all-in-one computers resurrected with new guts, including…

Everyone familiar with the arc of personal computers knows Commodore. The calculator…

• 1 min read

Verification

Join Us at FMCAD October 20-23

Are you deeply interested in formal and assertion-based verification technology?…

• less than a min read
Alok Jain , ABV , Functional Verification , Formal Analysis , formal , FMCAD , IEV , IFV

System, PCB, & Package Design 

What's Good About AMS Simulator New Design Templates? They’re in the SPB16.3 Release

What's Good About AMS Simulator New Design Templates? They're in the SPB16.3 Release…

• 1 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , AMS simulation , Design Entry , Schematic

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 2

My last blog entry began a series using quotes from Hollywood movies to illustrate…

• 2 min read
vPlan , verification planning , Verification IP modeling , metric-driven verification , MDV

SoC and IP

HP’s memristor finds a commercial semiconductor vendor: Hynix

The rumor at the recent Flash Memory Summit held earlier this month was that HP was…

• less than a min read

SoC and IP

Toshiba 24nm, 64-Gbit NAND Flash: Just a silly nanometer shorter

Toshiba announced today that it has initiated mass production of NAND Flash memories…

• less than a min read

SoC and IP

17 SSDs reviewed by Tom’s Hardware

We’re still at the stage where there can be appreciable differences in the performance…

• 1 min read

SoC and IP

Huawei talks Smart Memory at Hot Chips 22: “The only practical solution”

Last week saw the 22nd Hot Chips conference, held at held Stanford University, and…

• 3 min read

SoC and IP

A non-exhaustive list of 150 SSD vendors

A recent check of the Yahoo! Finance boards showed some skepticism about my previous…

• 1 min read

SoC and IP

PCM (now with carbon nanotubes!) programming current drops two orders of magnitu…

A fascinating Masters thesis written by Feng Xiong details the fabrication and testing…

• 1 min read

SoC and IP

Seagate and Samsung to jointly develop enterprise-class SSD controller -- a little…

A bit more than a week ago, HDD leader Seagate and NAND Flash leader Samsung jointly…

• 1 min read

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 1

True story: this series of blog posts is inspired by a dream. I recently gave a presentation…

• 3 min read
vPlan , verification planning , Verification IP modeling , metric-driven verification , MDV

SoC and IP

8 key takeaways for system design teams from the Flash Memory Summit

Cadence’s Senior Manager of Technical Communications and a longtime EDA observer…

• less than a min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Outputs Setup in ADE XL

Continuing on our exploration of ADE XL (see here and here for previous articles…

• 5 min read
IC 6.1 , Analog Simulation , analog , ADE , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About Capture Objects Look and Feel? You Can Change Them in SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (known as Capture) has some cool…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , Design Entry , PCB Capture , Schematic

SoC and IP

Kingston DDR3 RAM cracks 3Gtransfers/sec barrier, achieves 3.068 Gtransfers/sec amid…

Mix liquid nitrogen and Kingston’s HyperX DDR3-2333 SDRAM modules and you get 3068…

• 1 min read
CDNS - Fix Layout Hompage