Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Why The UVM Is Ready For Production Use Today -- Part 3

This is the final installment of my blog posts based on the three common questions…

• 1 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

Verification

Duolog Interview At DAC 2010, And The IP Integration Aspect Of EDA360

One virtue of events like DAC is that is provides an open forum for vendors to show…

• less than a min read
Cadence Connections , DAC , uvm , IP , IP-XACT , OVM , EDA360 , Duolog

SoC and IP

Specialty semiconductor foundry TowerJazz licenses “Y-Flash” IP to “leading” digital…

TowerJazz, the specialty semiconductor foundry created by the merger of Tower Semiconductor…

• 2 min read

System, PCB, & Package Design 

What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!

Current design technologies require extremely tight matching requirements right down…

• 1 min read
PCB , PCB Layout and routing , SPB16.3 , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Constraint Manager , via , "PCB design" , PCB design , Allegro PCB Editor

SoC and IP

Will Taiwan Innovation Memory Company (TIMC) become Taiwan’s NAND Flash Inc?

The Taiwan Innovation Memory Company (TIMC) was originally formed as the Taiwan Memory…

• 1 min read

Verification

Why The UVM Is Ready For Production Use Today - Part 2

In my last blog post , I talked about the three most common questions I heard at…

• 1 min read
DAC , uvm , OVM , VIP , EDA

SoC and IP

DRAM vendors look to 40nm process technology to keep DRAM profits flowing next y…

Taiwan Economic News reports that DRAM vendors will be bringing 4x nm process technologies…

• 1 min read

Verification

DAC Report: Interview With AMIQ And Update On Their “DVT” IDE

One of the benefits of the Design Automation Conference is the opportunity to follow…

• 1 min read
SystemVerilog , DAC , uvm , OVM ML , Functional Verification , OVM , EDA360 , e , OVM-e , Verilog , AMIQ , VHDL

Verification

DAC report: Video Interview With Zocalo

One of the benefits of the annual Design Automation Conference is the opportunity…

• 1 min read
DAC , ABV , Functional Verification , Formal Analysis , EDA360 , EDA , SVA , IEV , IFV

Verification

Why The UVM Is Ready For Production Use Today - Part 1

As I mentioned in my DAC report , I spent the largest percentage of my time at the…

• 2 min read
DAC , uvm , Functional Verification , OVM , VMM

Digital Design

DAC 2010 – A “Coming Out” Party For 3D-IC Design

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor…

• 2 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , 3D , stacked die , flip chip , PoP

SoC and IP

New Freescale ARM-M4 and ColdFire-based 32-bit microcontrollers feature on-chip nanocrystal…

June’s Microprocessor Report carries an article written by Editor-in-Chief Jim Turley…

• 3 min read

SoC and IP

Intel + Best Buy + SSD = Sign of the Times

Intel recently announced that Best Buy is now carrying its retail-boxed X25-M (mainstream…

• less than a min read

Verification

Tech Tip On Verification Environment Re-Use

Verification has come a long way this past year, the highlight of which is UVM. UVM…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , OVM , Plan and metrics management

Verification

DAC Perspective One Week Later

DAC in Anaheim last week was as busy as always, perhaps more so, and of course I…

• 2 min read
DAC , uvm , Functional Verification , OVM , EDA360 , Denali , MDV

Verification

IntelliGen Moving Into The Spotlight With Pgen Deprecation

Specman's new Aspect Oriented Generation Engine, IntelliGen, has now been in service…

• 1 min read
IntelliGen , Specman , VIP , EDA , e , Funcional Verification , team specman , specman elite , Aspect Oriented Programming , CMS , Incisive Enterprise Simulator (IES) , AOP , IES-XL

SoC and IP

Elpida, Powertech Technology, and UMC team up to mate SOCs and memory using 3D design…

The idea of 3D wafer stacking isn’t new. I wrote an article about 3D assembly of…

• 1 min read

SoC and IP

SanDisk’s WORM (write-once, read mostly) SD card can’t be altered once written. Good…

SanDisk has just unveiled a WORM (write-once, read mostly) variant of the ubiquitous…

• 1 min read

System, PCB, & Package Design 

What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements

A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor…

• 4 min read
PCB , PCB Layout and routing , SPB16.3 , Allegro 16.3 , SPB 16.3 , PCB Editor , Layout , via , "PCB design" , PCB design , Allegro PCB Editor , microvia , Allegro
CDNS - Fix Layout Hompage