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System Development Suite - Connecting Software to Hardware Design and Verificati…

I've been at CDNLive! EMEA watching demos of the newly announced System Development…

Jack Erickson 9 May 2011 • 2 min read

ECO , Virtual System Platform , TLM , hardware , System Design and Verification , C-to-Silcon , System Development Suite , software , SystemC , verification

Verification

Yes We Can...Do FPGA-Based Prototoyping

As part of this week's System Development Suite announcement , Cadence introduced…

Juergen57 6 May 2011 • 2 min read

RPP , Verification Computing Platform , prototyping , rapid prototyping , System Development Suite , Palladium XP , FPGA-based , Rapid Prototyping Platform , prototype , FPGA

Analog/Custom Design

Virtuoso Analog Design Environment XL – Embrace the Productivity

In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better , I wrote…

archive 6 May 2011 • 4 min read

parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , Analog Simulation , analog , IC 6.1.5 , ADE , ADEnalog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Parasitic analysis , Custom IC Design

Verification

Welcome to the Cadence Virtual System Platform

The announcement of the Cadence Virtual System Platform is a momentous event for…

jasona 5 May 2011 • 6 min read

Verification

Why Can’t You Write My Assertions for Me? - Part 3

My last two posts have dealt with various forms of automatic assertion creation…

tomacadence 4 May 2011 • 2 min read

conformal , ABV , Zocalo , Functional Verification , formal , CPF , CDC , Palladium , Incisive , assertion synthesis , assertions , Constraints , IEV , Formal verification , IFV , Assertion-based verification

Verification

Building Open Virtual Platforms - Bridging the Gap of Model Availability

Virtual prototypes promise to enable early software development, shorten system bring…

Steve Brown 4 May 2011 • 2 min read

TLM2 , Virtual System Platform , IP , TLM , Models , virtual prototypes , virtual platform , TLM 2.0 , System Development Suite , architectural , embedded software , VSP , Multi-Core , SystemC analysis , SystemC , Modeling , multicore , architect , System Design and Verification

Verification

The Challenge of System Integration and Bring-Up

In the last few years, I have talked with many companies and analysts and consistently…

Ran Avinun 3 May 2011 • 3 min read

prototyping , Bring-up , Acceleration , validation , Embedded Systems Conference , System Design and Verification , System Development Suite , EDA360 , System C , Team ESL , Emulation , virual platform , virtual protoype , Verification Acceleration , CDNLive! , Hardware/software co-verification , system integration

Analog/Custom Design

SKILL for the Skilled: Sorting With SKILL++

In the previous couple of SKILL for the Skilled postings we looked at some of the…

Team SKILL 3 May 2011 • 6 min read

Team SKILL , programming , functions , sort , Virtuoso , SKILL++ , sorting , SKILL

System, PCB, & Package Design

Allegro 16.5 Powers up Allegro PCB PDN Analysis

Attendees of DesignCon 2011 received a sneak peek , and now Allegro PCB designers…

TeamAllegro 29 Apr 2011 • 1 min read

PCB SI , PDN , Power Integrity , PCB power integrity , Allegro 16.5 , Power Delivery Network , PCB Signal integrity , power

Verification

Video: DVCon and DVClub Case Study: NextOp’s BugScope for Assertion-Based Verification…

Attendees of the Silicon Valley DVClub this past Tuesday were treated to some real…

TeamVerify 28 Apr 2011 • less than a min read

NextOp , ABV , videos , Functional Verification , BugScope , DVClub , broadcom , Jing Lee , DVcon , assertion synthesis , Yuan Lu , Assertion-based verification

Analog/Custom Design

Thing You Didn't Know About Virtuoso: Redux

After a long break, I'm going to try to venture back into the blogosphere, starting…

stacyw 27 Apr 2011 • 1 min read

Virtuoso IC6.1.5 , Search Assistant , IC 6.1 , Navigator , IC 6.1.5 , Virtuoso , Property Editor , Custom IC Design , Schematic-driven Layout , Schematic

System, PCB, & Package Design

DDR3 Design-in Challenges Tackled by SoC Realization With Allegro PCB SI

Allegro 16.5 is another step forward for Cadence towards the realization of the EDA360…

TeamAllegro 27 Apr 2011 • 2 min read

PCB , design-in kit , EDA360 , Allegro 16.5 , bus analysis , TeamAllegro , memory IP , SoC Realization , TimingDesigner , SPB16.5 , DDR3

Verification

Why Can’t You Write My Assertions for Me? - Part 2

In my last post , I described three different types of automatic assertions: those…

tomacadence 25 Apr 2011 • 3 min read

conformal , NextOp , ABV , Functional Verification , formal , CPF , CDC , Palladium , Incisive , assertion synthesis , assertions , Constraints , IEV , Formal verification , IFV , Assertion-based verification

Verification

Video Easter Egg: Incisive Formal Verifier and SVA driving a Rubik's Cube robot

Just in time for Easter, Team Verify's Apurva Kalia, Manu Chopra, and Suman Ray of…

TeamVerify 21 Apr 2011 • 1 min read

Suman Ray , ABV , Apurva Kalia , Formal Analysis , Easter , formal , Manu Chopra , SVA , Verilog , Lego , assertions , egg , robot , ARM , IEV , Rubik's Cube , Formal verification , IFV , Assertion-based verification

Verification

Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes…

A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with…

Marcgr 20 Apr 2011 • 3 min read

controller IP , security , IP , Princeton , Memory , VIP , encryption , SoC , memory IP , DRAM , Denali , DDR , reboot , MMAV

System, PCB, & Package Design

What's Good About Allegro PCB Editor Flipping and Origins? Look to SPB16.3 and See

There are a couple quick new SPB16.3 Allegro PCB Editor features to mention this…

Jerry GenPart 19 Apr 2011 • 2 min read

PCB , PCB Layout and routing , SPB16.3 , flipping , SPB 16.3 , flip design , PCB Editor , Layout , design , "PCB design" , PCB design , Allegro PCB Editor , Allegro

Analog/Custom Design

Analog IP Verification - A Reference Guide to Practices Used

I have had a lot of discussions recently around improving the final integration of…

JohnPierce 18 Apr 2011 • 1 min read

AMS , Analog Design Environment , mixed-signal simulators , Analog Simulation , analog , IC 6.1.5 , ADE , assertion , AMS simulation , assertions , mixed signal

Analog/Custom Design

Will Evolving Language Standards Address Mixed-Signal Verification Problems?

Mixed-signal verification has been one of the hottest topics in the past year, and…

archive 18 Apr 2011 • 6 min read

SystemVerilog , AMS , assertion-based , SV-DC , analog , ADE , Mixed-Signal , SVA , DMS , Accellera , mixed signal , A-SVA

System, PCB, & Package Design

What's Good About Capture CIS Relational Tables? SPB16.3 Has a Few New Enhancements

If you have defined relational fields in your Allegro Design Entry CIS configuration…

Jerry GenPart 13 Apr 2011 • 2 min read

SPB16.3 , Allegro Design Entry , data management , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , relational tables , design data management , design , OrCAD , Component Information Portal (CIP) , Librarians , library , PCB Capture , Schematic

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