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Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI
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Blog - Post List

Latest blogs

Verification

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

In the continuing effort to make high-level synthesis more viable to mainstream RTL…

• 1 min read
CTOS , TLM , C-to-Silicon , Synthesis , HLS

SoC and IP

Hitachi’s Z HDDs: Will 2.5mm less height make a difference? For SSDs?

Hitachi just shaved 2.5mm off of the top of its 2.5-inch laptop hard drives, producing…

• 1 min read

SoC and IP

More details on and system-design implications of the Hitachi-LG Data Storage HyDrive…

As discussed last week in this blog, Hitachi-LG Data Storage (HLDS)--an OEM vendor…

• 3 min read

System, PCB, & Package Design 

What's Good About AMS Simulator And Cursors? You’ll Need The SPB16.3 Release To See

With the SPB16.3 release of AMS Simulator , several new cursor enhancements are available…

• 1 min read
AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Schematic

SoC and IP

ST Microelectronics’ SPEAr1300 embedded MCU features 600MHz dual-core ARM Cortex…

A few days ago, this blog discussed the “big resistor” model of SDRAM power consumption…

• 2 min read

Verification

TLM 2.0 As Part Of The EDA360 Vision

Ann Steffora Mutschler recently covered in her blog the progress the industry has…

• 1 min read
TLM , virtual platform , TLM 2.0 , EDA360 , virtual prototype , SystemC , Synthesis , System Design and Verification

System, PCB, & Package Design 

Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence…

Is there anyone who does not carry a mobile communication device anymore? Sending…

• 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , Allegro 16.3 , APD , webinar , SI analysis and modeling

SoC and IP

How does a hybrid SSD/optical drive make sense?

Some combinations like chocolate with peanut butter, ice cream with peanuts and chocolate…

• 1 min read

Verification

EDA360 Is More Than Design IP Plus Software Drivers

I checked my Linked-In messages the other day and saw a survey by Girish Patil with…

• 2 min read
IP , Functional Verification , Virtual Chips , Phoenix , inSilicon , VIP , EDA360 , Sand

SoC and IP

Does Samsung really scare Japan? EETimes’ Junko Yoshida thinks so.

EETimes' Junko Yoshida just published an article titled “5 reasons why Samsung scares…

• 1 min read

SoC and IP

Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption

Too many DRAM choices. If you want low power DRAM, do you choose LPDDR1, LPDDR2,…

• 2 min read

SoC and IP

OCZ Enyo USB 3.0 SSD reviewed by PC Perspective video

Earlier, we covered the announcement of OCZ’s Enyo USB 3.0 external SSD. Now PC Perspective…

• less than a min read

SoC and IP

InfoWeek video series chronicles storage and SSD Evolution. Part 1 runs 8 minutes…

Can you spare nine minutes to get a really good grounding in SSD concepts? No? How…

• 1 min read

System, PCB, & Package Design 

What's Good About Browsing For Power Pins in Capture? It's In SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (Capture) now allows you to browse…

• 1 min read
"capture CIS" , Capture CIS' , Design Entry CIS , OrCAD Capture , SPB 16.3 , Capture CIS , Capture-CIS , OrCAD , Design Entry , Schematic

SoC and IP

Squeeze bandwidth inefficiencies out of DDR DRAMs in memory subsystem designs

This blog starts with a simple, sad truth: DDR DRAMs are naturally inefficient. If…

• 6 min read

Digital Design

Mixed Signal: Why The Sudden Attention?

With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors…

• 2 min read
DAC , SoC , Mixed-Signal , Digital Implementation , mixed signal

SoC and IP

Why is it so difficult to interface with DRAMs?

One of the maxims in the world of system design is that it has always been relatively…

• 3 min read

Verification

The Future of OVM, VMM, and UVM

In my last blog , I took a look back at the history of how we got to the first delivery…

• 3 min read
SystemVerilog , uvm , methodology , Functional Verification , Open Verification Methodology , OVM , VIP , Accellera , Accellera VIP TSC , VMM

SoC and IP

Google TV and Intel’s CE4100 SOC (Sodaville)--is this a world-beating combo or what…

Having vacuumed up most of the world’s very large and growing Internet advertising…

• 5 min read
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