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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

SoC and IP

Micron using ONFI 2.1 and SATA 3.0 to leapfrog Enterprise SSDs over HDD performa…

PCWorld reports that Micron will soon be rolling out Enterprise-class SSDs based…

• 1 min read

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Groups? Look to SPB16.3 and See!

With the Allegro PCB Editor SPB16.3 release, you can now allow groups to have elements…

• 1 min read
PCB design

Verification

Specman-SimVision webinar on April 22 (next week!)

We interrupt Corey's excellent "When Less Is More" series to announce a Specman-SimVision…

• 1 min read
IEEE 1647 , debug , Functional Verification , simvision , e , multi-language , IES-XL

SoC and IP

Eurocom’s D900F Panther Notebook with 6-core Intel i7-980X processor: the shape of…

With all the talk of DRAM growth in 2010, you might wonder what’s driving the consumption…

• 3 min read

SoC and IP

More signs of spring for the 2010 DRAM market

Earlier, we reported on the appearance of several good economic signs springing up…

• 1 min read

Verification

Hate Writing Assertions? No problem: let Automatic Formal Analysis do the work

OR: “Leverage automatic checks extracted from designs without writing a single assertion…

• 4 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

Verification

New Blog: All About Integrated formal, Simulation, and Assertion-Based Verification…

End-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV…

• 1 min read
ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , OVM , Incisive , Twitter , MDV , IEV , IFV

SoC and IP

Apple iPad: no LPDDR2?

Guest Blogger: Marc Greenberg, Technical Marketing Director By now it seems…

• 3 min read

SoC and IP

Good times for DDR2 and DDR3 DRAM: Think Memcon 2010

Several more bits of good DRAM news today appearing in DigiTimes and elsewhere point…

• 1 min read

System, PCB, & Package Design 

What's Good About Windows 7? You'll Need SPB16.3 To See!

OK, OK - I'm sure you don't "need" SPB16.3 to see all the cool whiz-bang features…

• 1 min read
SPB 16.3 , PCB design , CDNLive! , windows 7 , Allegro

SoC and IP

OCZ Technology unleashes 4th-generation PCIe-based SSD: 512Gbytes to 2Tbytes

Yesterday, high-performance PC component developer and vendor OCZ Technology rolled…

• 1 min read

SoC and IP

DRAMeXchange says iPad intro will moderate NAND Flash market

By Steve Leibson, Technology Evangelist, Denali Software The recent, very successful…

• 2 min read

SoC and IP

DDR3/DDR2 price crossover reached

Guest Blogger: Marc Greenberg, Director, Technical Marketing The day is finally…

• 1 min read

Verification

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog…

In my last post I wrote some packet generation code to validate the claim that e…

• 4 min read
IEEE 1647 , SystemVerilog , Functional Verification , OVM , OVM e , CDV , OVM SV , e , coverage driven verification (CDV) , Aspect Oriented Programming , AOP , IES-XL

Digital Design

IR Drop Analysis: It's Not Really Necessary, Is It?

I was recently asked by an engineering manager if running IR drop analysis was really…

• 2 min read
VDD , VDD I/O , Digital Implementation , IR drop , EM Failures

Analog/Custom Design

Things You Didn't Know About Virtuoso: It's Video Time!

Just a quick post to let you know that there have recently been a whole truckload…

• 1 min read
IC 6.1 , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About Support Service And Design Bureau Providers? AcAe Can Help!

I usually discuss our SPB solution technical capabilities in my weekly blogs, but…

• 2 min read
PCB , design bureau , AcAe , Layout , PCB design , Allegro

Verification

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines…

• 3 min read
IEEE 1647 , SystemVerilog , Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , e , OOP , ClubT , Aspect Oriented Programming , AOP , IES-XL

Digital Design

My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden…

• 3 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP
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