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Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI

Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Digital Design

Understanding Clock Net Markings in SoC-Encounter

I'm happy to report that the Digital Implementation Forums are picking up momentum…

• 3 min read
dbGet , Digital Implementation forums , CTE-TCL , encounter , clocks , saveClockNets

System, PCB, & Package Design 

Breaking down the 'virtual' wall

In the last 3-4 months I have seen, and been involved in, a flurry of discussions…

• 1 min read
IP , cadence , Allegro 16.2 , IC Packaging & SiP design , wirebond profile library , Kulicke & Soffa

System, PCB, & Package Design 

Verifying multi-technology chips-in-a-SiP, fact or fiction?

With everyone talking about System-in-Package (SiP), one challenge that often gets…

• less than a min read
Analog and RF SiP design , IC Packaging & SiP design , IC Package Physical layout and co-design

Verification

iPhone 3G issues - result of HW/SW-co-verification?

In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G…

• 2 min read
Richard Windsor , Infineon 3G chipset , Infineon , System Design and Verification , iPhone 3G , Nomura

Verification

ESL gets a new taker

Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification…

• less than a min read
High-Level Synthesis , IC Design and Verification , CDNLive! Silicon Valley 2008

RF Engineering

Tip of the Week: New nport parameter ( dcextrap ) for modeling longer transmission…

There is a new nport parameter, dcextrap, available in MMSIM 6.2.1. The values are…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

SPB 16.2 release - Constraint Driven HDI PCB Design Flow

Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families…

• 3 min read
PCB Layout and routing , NVIDIA , Harris , High-Density Interconnect , PCB design , Allegro PCB Editor , OrCAD PCB Editor , HDI

Verification

Is Concurrent Engineering actually getting worse?

Today I'm taking a few minutes to jot down a few recent observations about the state…

• 3 min read
Concurrent Engineering , System Design and Verification , ISX

Verification

OVM - The Methodology for Enabling an Industry-wide VIP Eco-System

As the leader of the Cadence OVM development team, I was reading Richard Goering…

• 3 min read
SystemVerilog , OVM Professionals Network , Verification methodology , Functional Verification , Open Verification Methodology , OVM , Verification IP modeling , eRM , OVMWorld

System, PCB, & Package Design 

What's good about database parameters and XML import/export?

In the SPB16.01 release, you can now import/export database parameters from Allegro…

• 1 min read
PCB Layout and routing , XML import/export , SPB , PCB design , Allegro PCB Editor , SPB16.01 , OrCAD PCB Editor

RF Engineering

Simulating MOS Transistor ft

One other question that you might ask is, this approach works for bipolars but what…

• less than a min read
bipolar transistor , MOS transistor , RF design

System, PCB, & Package Design 

PartMiner Launches Unique Integration with Cadence OrCAD Capture

Cadence OrCAD Capture is integrated with PartMiner. As a long time EDA librarian…

• 1 min read
Steven Kamin , OrCAD Capture , PartMiner , PCB design

Verification

OVM Leaves the Nest

OK JL , one more marketing post, but this is a good one and even hints at technical…

• less than a min read
Functional Verification , OAG , OVM , OVM Advisory Group , OVMWorld

System, PCB, & Package Design 

What's good about Capture-CIS Digi-Key Integration?

So, what's good about Capture-CIS Digi-Key Integration? Quite a bit actually! This…

• 1 min read
Capture CIS , PCB design , Component Information Portal (CIP) , Digi-Key Integration

Digital Design

See you at CDNLive! Silicon Valley

Are you planning to attend this year's CDNLive! Silicon Valley 2008? Please leave…

• less than a min read
cadence.com community , First Encounter , CDNLive!

Verification

Putting a face on the OVM

As I recently blogged , there appears to be growing buzz over the Open Verification…

• 1 min read
CDNLive , Open Verification Methodology , OVM

RF Engineering

Tip Of the Week: analogLib mtline now has a cross sectional viewer when Type of Input…

Many users have indicated that it is challenging to correctly enter complex transmission…

• less than a min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Verification

Design space exploration

In his latest blog post Space Exploration ... design is , Grant Martin said that…

• 1 min read
high-level synthesis adoption , System Design and Verification , C-to-Silicon Compiler

Verification

Report from the CDV techtorials in SoCal

To follow-up on my previous post on the techtorials, I'm posting some photos from…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , coverage driven verification (CDV) , eRM
CDNS - Fix Layout Hompage