Logic Design Blogs

Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to efficiently...

Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.

The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed...

Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows....

How to use Encounter® RTL Compiler support Interface Logic Models during synthesis.

With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences...

Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and...

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via...

Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL...

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis...

It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design...

Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence...

If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that...

The latest major release of Encounter ® RTL Compiler is available for download (look for "RC101"). Some of the highlights include: Quality of Silicon improvements. A lot of work continues to go into improving results, especially physical...

Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting...

At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies...

This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's Day from my proud son...

With a tagline of "Go beyond your imagination", it was pretty clear that this year's CDNLive! EMEA event would not be a typical user conference. Of course it also kicked off just days after our EDA360 launch, so there was a lot of buzz...

It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its...

If you've seen all the buzz this week about Cadence's EDA360 vision for a major shift in the EDA industry, you may be wondering as a logic designer - "where do I fit? Does Cadence still care about what I do?" The short answer is...

If you are not yet familiar with the ChipEstimate.com site.....first, why not? It is the leading portal for design IP with over 200 IP suppliers and over 8,000 components available. The team behind the site has been hard at work making it an even more...

Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results...

Here in the U.S., in recent years we've seen all kinds of commercials on TV for prescription pharmaceuticals. Needless to say, they have to figure out how to sell something that is very intangible in most cases. This is not unlike algorithm-oriented EDA...

There has been a lot of talk recently about improving synthesis predictability by passing forward "guides" to physical design. This was something that we investigated doing in RTL Compiler, too. That was 2003. So whenever I get asked by folks if we would...

Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other...