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New Technical Resources for Encounter Test Users on http://support.cadence.com
By
MJ Cad
|
19 Aug 2014
Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to efficiently...
0 Comments
Tags:
Encounter Test
|
test generation
|
RAK
|
library models
|
ATPG
|
Encounter diagnostics
Learn Logic built-in self-test (LBIST) macro generation and insertion at your desk
By
SumeetAggarwal
|
16 Apr 2014
Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.
0 Comments
Tags:
Encounter Test
|
Encounter DFT Architect
|
RAK
|
OPCG
|
JTAG
|
rtl compiler
|
Encounter Diagnostic
|
rc
|
LBIST
|
ATPG
RTL Compiler (RC) Timing Analyzer (RTA) Flow
By
SumeetAggarwal
|
17 Feb 2014
The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed...
0 Comments
Tags:
rc compiler
|
timing bin
|
RC-Physical
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timing analyzer
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rta
|
RAKs
New Rapid Adoption Kit on Encounter RTL Compiler: RC-Physical Low Power Flow
By
SumeetAggarwal
|
12 Jan 2014
Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows....
0 Comments
Tags:
RC Physical
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RC-Physical Low Power Flow
|
front-end design
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RAK
|
rtl compiler
|
Rapid Adoption Kits
|
RC -Physical Flow
Encounter® RTL Compiler Hierarchical ILM (Interface Logic Model) Flow
By
SumeetAggarwal
|
6 Jan 2014
How to use Encounter® RTL Compiler support Interface Logic Models during synthesis.
0 Comments
Tags:
hierarchical VLSI implementation flows
|
EDI
|
synthesis tips for RTL compilers
|
synthesis eda tools
|
Interface Logic Model
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ILM
|
RAK
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rtl compiler
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synthesis flow
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top-level synthesis
|
rc
|
routing resources at SoC level
|
Placement
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Rapid Adoption Kits
|
hierarchical synthesis
RTL Compiler Beginner’s Guides Available on Cadence Online Support
By
SumeetAggarwal
|
12 Nov 2013
With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences...
0 Comments
Tags:
RC Logfile Diagnostic
|
DFT
|
RC Migration
|
rtl compiler
|
low power implementation
|
rc
|
Physical Synthesis
|
Integrating CPF
Discover Programmable MBIST and Boundary Scan Insertion and Verification Flows Through RAKs
By
SumeetAggarwal
|
9 Aug 2013
Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and...
0 Comments
Tags:
Encounter Test
|
boundary scan
|
Encounter True-Time Test
|
Programmable MBIST
|
encounter
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rtl compiler
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Insertion and Verification Flow
|
Encounter Diagnostic
|
rc
|
PMBIST
Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose
By
Kenneth Chang
|
27 Nov 2012
Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via...
0 Comments
Tags:
front end
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conformal
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Encounter Test
|
cadence
|
front-end design
|
Kenneth Chang
|
encounter
|
Logic Design
|
rtl compiler
|
front-end summit
Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler
By
SumeetAggarwal
|
7 Aug 2012
Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL...
0 Comments
Tags:
Functional Verification
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fixing timing violations
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boundary optimizations
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Logic Design
|
rtl compiler
|
optimizations
|
rc
|
Synthesis
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)
By
SumeetAggarwal
|
24 Jul 2012
A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis...
0 Comments
Tags:
conformal
|
EDI
|
Encounter Test
|
customer enablement
|
LEC
|
Incisive Enterprise Simulator
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Incisive
|
Incisive Unified Simulation
|
Test
|
Logic Design
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rtl compiler
|
Logic synthesis
|
ATPG
|
Synthesis
|
Rapid Adoption Kits
|
RAKs
|
verification
8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
By
David Stratman
|
20 Jun 2011
It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design...
0 Comments
Tags:
design comipler
|
DC
|
DAC
|
Low Power
|
deepchip
|
methodology
|
cadence
|
RTL
|
CPF
|
power management
|
encounter
|
Logic Design
|
rtl compiler
|
digital
|
Cooley
|
rc
|
Logic synthesis
|
Digital End-to-End
|
Synthesis
|
synopsys
|
Common Power Format
Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line
By
Kenneth Chang
|
7 Feb 2011
Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence...
0 Comments
Tags:
ECO
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conformal
|
ECOs
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encounter
|
Logic Design
|
ECO Designer
|
Digital End-to-End
|
Conformal ECO
New Era Of SoC Design – Still Enabled By Logic Designers
By
Jack Erickson
|
8 Jul 2010
If you were unable to attend Embedded/SoC Enablement Day at DAC, I encourage you to check out Richard Goering's writeup on the new era of SoC design being driven by applications . It describes how Gadi Singer of Intel discussed new TVs that...
0 Comments
Tags:
TLM
|
EDA360
|
rtl compiler
|
C-to-Silicon
|
Silicon Realization
|
SoC Realization
|
Synthesis
Now Available: Encounter RTL Compiler 10.1
By
Jack Erickson
|
28 Jun 2010
The latest major release of Encounter ® RTL Compiler is available for download (look for "RC101"). Some of the highlights include: Quality of Silicon improvements. A lot of work continues to go into improving results, especially physical...
1 Comments
Tags:
Logic Design. Power Shut-Off
|
RTL Compiler 10.1
|
multi-vt
|
turnaround time
|
Synthesis
TSMC Reference Flow Adds TLM Support -- Here's Why
By
Jack Erickson
|
11 Jun 2010
Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting...
0 Comments
Tags:
TLM
|
EDA360
|
rtl compiler
|
C-to-Silicon
|
Silicon Realization
EDA360: Enlightenment for Silicon Test
By
Ed JM
|
21 May 2010
At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies...
0 Comments
Tags:
EDA360
|
Test
|
Logic Design
|
ATPG
Friday Fun: InCyte Chip Estimator infomercial
By
Jack Erickson
|
14 May 2010
This is our second (and last, for now) foray into the genre of cheesy American commercial advertisement. Here was our first attempt . I've been fascinated with the infomercial approach ever since I received "The ShamWow" for Father's Day from my proud son...
1 Comments
Tags:
Logic Design. Power Shut-Off
|
friday fun
|
incyte
|
chip planning
|
chip estimate
CDNLive! EMEA: Taking logic design beyond the imagination
By
Jack Erickson
|
6 May 2010
With a tagline of "Go beyond your imagination", it was pretty clear that this year's CDNLive! EMEA event would not be a typical user conference. Of course it also kicked off just days after our EDA360 launch, so there was a lot of buzz...
0 Comments
Tags:
Automotive
|
ChipEstimate.com
|
Logic Design
|
CDNLive!
Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp
By
Ed JM
|
29 Apr 2010
It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its...
4 Comments
Tags:
DFT
|
test escapes
|
yield gap
|
nanometer
|
physical defect analysis
|
power test
|
precision diagnostics
|
low power test
|
Ed Malloy
|
yield optimization
|
yield diagnostics
|
PDA
|
root cause
|
defect detection
|
Prediction
|
SDD
|
Test
|
TMSC
|
Logic Design
|
QoS
|
Semiconductor
|
test mode
|
defect testing
|
diagnostics
|
volume diagnostics
|
yield
|
DFM
What does EDA360 mean for logic designers?
By
Jack Erickson
|
28 Apr 2010
If you've seen all the buzz this week about Cadence's EDA360 vision for a major shift in the EDA industry, you may be wondering as a logic designer - "where do I fit? Does Cadence still care about what I do?" The short answer is...
0 Comments
Tags:
IP
|
TLM
|
EDA360
The new ChipEstimate.com: The place to be for IP
By
Jack Erickson
|
21 Apr 2010
If you are not yet familiar with the ChipEstimate.com site.....first, why not? It is the leading portal for design IP with over 200 IP suppliers and over 8,000 components available. The team behind the site has been hard at work making it an even more...
0 Comments
Tags:
Verification IP
|
ChipEstimate.com
|
IP
|
Logic Design
|
incyte
Logic Design and Test Design: Do they need each other?
By
Ed JM
|
16 Apr 2010
Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results...
0 Comments
Tags:
DFT
|
test escapes
|
quality
|
RTL Compiler 9.1
|
logic design
|
power test
|
false fail
|
power management
|
Test
|
Logic Design
|
digital
|
voltage drop
|
FED
|
power estimation
|
test mode
|
Logic synthesis
|
defect testing
|
yield
|
blog logic design
|
power
|
fault model
|
design for manufacturing
Friday Fun: Multi-objective optimization for your iteration problem
By
Jack Erickson
|
16 Apr 2010
Here in the U.S., in recent years we've seen all kinds of commercials on TV for prescription pharmaceuticals. Needless to say, they have to figure out how to sell something that is very intangible in most cases. This is not unlike algorithm-oriented EDA...
0 Comments
Tags:
DFT
|
RC-Physical
|
friday fun
|
rtl compiler
|
Timing Closure
|
power
Why physical guides are like Kramer
By
Jack Erickson
|
12 Apr 2010
There has been a lot of talk recently about improving synthesis predictability by passing forward "guides" to physical design. This was something that we investigated doing in RTL Compiler, too. That was 2003. So whenever I get asked by folks if we would...
0 Comments
Tags:
RC-Physical
|
Physical Prediction
|
Seinfeld
|
rtl compiler
|
Physical Synthesis
What Madonna Can Teach You About Chip Design
By
Jack Erickson
|
26 Mar 2010
Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other...
1 Comments
Tags:
Apple
|
TLM
|
Jack Erickson
|
Madonna
|
IBM
|
RTL
|
Logic Design
|
digital
>