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Latest Blog Posts

  • System, PCB, & Package Design : IC Packagers: Copy and Paste Refresh in 17.4

    Tyler
    Tyler
    The most common operations in any tool are probably adding, moving, deleting… plus copying and pasting. That we all are familiar with Control-C and Control-V being shortcuts to these actions speaks to their applicability across tools we use ev...
    • 10 Dec 2019
  • Breakfast Bytes: Cadence at CES 2020: Tensilica Everywhere

    Paul McLellan
    Paul McLellan
    Once again, Cadence will be at CES in Las Vegas. It takes place January 7 to 10, 2020, the start of a new decade. I wonder what electronic marvels we will see before 2030 rolls around. We will be in the south hall of the Las Vegas Convention Center (...
    • 10 Dec 2019
  • Analog/Custom Design: Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part IV

    Kabir
    Kabir
    This is the fourth blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. This part highlights how EM analysis in Virtuoso is compared with other third-party tools in terms of accuracy, performance, capacity, memory consumption, and usability.
    • 9 Dec 2019
  • Breakfast Bytes: Xcelium Is 50% Faster on AWS's New Arm Server Chip

    Paul McLellan
    Paul McLellan
    At Re:invent, Amazon AWS announced Graviton 2, their second-generation Arm server chip. In the AWS news blog, written by Jeff Barr, AWS Chief Evangelist, he provides details. Today I would like to give you a sneak peek at the next generation of Arm-...
    • 9 Dec 2019
  • 定制IC芯片设计 : Virtuosity: 针对高阶工艺节点器件级布线的工具— 干线-干线网状布线工具

    Parula
    Parula
    本博客强调了干线-干线网状布线功能的重要性,它不仅为定制器件级的布线提供了解决方法,还提高了版图设计师们的工作效率.
    • 8 Dec 2019
  • Verification: Cashing the PSS Promises

    Sharon
    Sharon
    A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...
    • 8 Dec 2019
  • Breakfast Bytes: Sunday Brunch Video for 8th December 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/3gP0Z02MVps Made at Salinas River State Park (camera Carey Guo) Monday: The Photonics Summit 2019: Hybrid Lasers Tuesday: Cadence to Acquire AWR Wednesday: "If You Can Get Your Ship into Orbit, You're Halfway to An...
    • 8 Dec 2019
  • Breakfast Bytes: System in Package, Why Now?

    Paul McLellan
    Paul McLellan
    At HOT CHIPS this summer, one of the things I noticed was just how many of the designs being presented were in some form of 3D packaging with multiple die. I wrote about many of them in my post HOT CHIPS: Chipletifying Designs. At last year's HOT...
    • 6 Dec 2019
  • Digital Design: Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells and IO Cells

    Aravind  R
    Aravind R
    Let’s read how you can use the Liberate Variety statistical characterization solution of the Cadence Liberate Characterization Portfolio for generating the statistical characterization models for standard cell libraries.
    • 5 Dec 2019
  • 定制IC芯片设计 : Virtuosity: 针对高级工艺节点器件级布线的工具 – Generate Trunks

    Parula
    Parula
    Trunk Generation 创新功能,不仅实现干线自动化,提高生产效率,还提供完整的Pin to Trunk 流程的自定义选项.
    • 5 Dec 2019
  • Breakfast Bytes: Photonics Summit: Lumerical-Cadence Flow

    Paul McLellan
    Paul McLellan
    James Pond, the CTO of Lumerical, wrapped up the Photonics Summit recently. He started by giving an overview of the Lumerical-Cadence flow but the real focus of his short presentation was creating robust designs using photonics inverse design, or PID...
    • 5 Dec 2019
  • 定制IC芯片设计 : Virtuosity: 针对高阶工艺节点的器件级布线工具 — Finish Trunk

    Parula
    Parula
    本博客是该系列博客的第一篇,将介绍Finish Trunk 命令,如何实现器件级的布线需求,它并不算是新功能,但可被认为是又一突破性功能.
    • 4 Dec 2019
  • Breakfast Bytes: "If You Can Get Your Ship into Orbit, You're Halfway to Anywhere"

    Paul McLellan
    Paul McLellan
    I planned on using the 50th anniversary of Apollo 12 as a hook for this blog, but as it happened I was sick that week, so never wrote it, and my post missed its "launch window". Apollo 12 was from November 14 to 24,1969. I wrote ...
    • 4 Dec 2019
  • System, PCB, & Package Design : Search Faster and Smarter in Release 17.4-2019

    Rachna2018
    Rachna2018
    Allegro and OrCAD 17.4-2019 products come with the latest version of CDNSHelp. In this post, I will quickly share the changes made in this release, that will make things much simpler and before you realize it, your content searches will give you better results, and you get more done. Or, know more about what ...
    • 3 Dec 2019
  • System, PCB, & Package Design : IC Packagers: The Third Dimension of 17.4 IC Packaging

    Tyler
    Tyler
    If you’ve run the 17.4 release, you have probably seen two 3D rendering tools – 3D Viewer and 3D Canvas – present in the View menu. Why are there two? That’s a good question, and the answer lies in the type of design you ...
    • 3 Dec 2019
  • Breakfast Bytes: Cadence to Acquire AWR

    Paul McLellan
    Paul McLellan
    Yesterday Cadence announced that it has signed an agreement to acquire AWR from National Instruments (NI). Cadence will pay approximately $160M and about 110 AWR employees will join us. The acquisition is expected to close in Q1 2020 after regulatory...
    • 3 Dec 2019
  • Breakfast Bytes: The Photonics Summit 2019: Hybrid Lasers

    Paul McLellan
    Paul McLellan
    Recently, Cadence held the fourth Photonics Summit and Workshop over two days. I attended the summit. The workshop was hands-on designing an RF photonics front-haul implementation. In fact, that was the focus of the whole summit, which was title...
    • 2 Dec 2019
  • System, PCB, & Package Design : Experience the Power of OrCAD with Its Trial Version

    AllegroReleaseTeam
    AllegroReleaseTeam
    OrCAD Trial 2019 is out. Download and use the full power of the latest release of OrCAD Capture CIS, PSpice, PCB Editor, OrCAD Sigrity ERC, and more, for up to 30 days. Designed to accelerate your productivity, this is a ...
    • 28 Nov 2019
  • System, PCB, & Package Design : IC Packagers: Materially Good Changes in 17.4

    Tyler
    Tyler
    You should be getting used to the new 17.4 release at this point. I am willing to bet there are still exciting new improvements that you haven’t found yet. Today, allow me to show off the new materials editor.  It is likely you don’t...
    • 26 Nov 2019
  • System, PCB, & Package Design : BoardSurfers: Installing on Windows is as Easy as Updating Apps on your Smart Phone

    Sanjiv Bhatia
    Sanjiv Bhatia
    Did you know that you can download and install available Cadence Allegro and OrCAD product releases and updates on Windows in an easy way using Cadence Download Manager? Yes, no more visiting the downloads.cadence.com site to check for...
    • 26 Nov 2019
  • Analog/Custom Design: Virtuosity: Sharing Expressions between Pre- and Post-Layout Simulations

    Arja H
    Arja H
    This has been an age old problem, you extract your design and get a DSPF file, then you want to run simulation in Virtuoso ADE Assembler, or Virtuoso ADE Explorer, using that DSPF file, but you find that none of your expressions evaluate. That's because the design is flat in the DSPF file, plus the extractor probably added prefixes to devices, changed the finger delimiters and changed the case of nets etc. You probably…
    • 26 Nov 2019
  • PCB、IC封装:设计与仿真分析: 版本升级:Sigrity 2019、Allegro/OrCAD 17.4现已发布

    SDA China
    SDA China
    space Sigrity 2019主要性能升级 新系统级分析工具:Celsius Thermal Solver 系统级电热协同仿真 Sigrity 2019版本引入Cadence® Celsius Thermal Solver工具,可以为从集成电路(IC)到实体外壳的整个电子系统体系提供完整的电热协同仿真。 Celsius Thermal Solver工具使用创新的多物理场技术来检测和解决热合规问题。通过将固体结构的有限元分析(FEA)与流体的计算流体力学(CFD)相结合,仅使用...
    • 22 Nov 2019
  • Breakfast Bytes: Implementing Arm Hercules with Digital Full Flow

    Paul McLellan
    Paul McLellan
    At Arm TechCon, there was a joint presentation by Arm, Cadence, and Samsung Foundry about implementing Arm's next-generation high-performance CPU in Samsung's 5nm process. The diagram below, from Arm's segment of the presentation, shows how the whole...
    • 22 Nov 2019
  • Digital Design: Library Characterization Tidbits: Basics of Standard Cell Characterization and More

    AbhaRawat
    AbhaRawat
    Characterization of standard cell libraries using the Liberate Characterization solution is broadly divided into five stages. Read this blog to know about the related basics and the step-by-step procedure.
    • 20 Nov 2019
  • Breakfast Bytes: 2nd WOSET Workshop on Open-Source EDA

    Paul McLellan
    Paul McLellan
    During ICCAD earlier in the month, there was the 2nd WOSET, which stands for Workshop on Open-Source EDA Technology. I wasn't there but Anton Klotz, who runs the Cadence Academic Network in Europe, was there and this is based on his report. I wro...
    • 20 Nov 2019
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