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Breakfast Bytes: Intel IDM 2.0

Paul McLellan

You've probably read in the press that Intel's new CEO, Pat Gelsinger, laid out his vision for Intel's future last week. You probably also know that, as he put it, "I've spent four decades in this industry, three of them here at ...
- 29 Mar 2021
Analog/Custom Design: Spectre Tech Tips: Detecting Leakage Path Current Hotspots

Stefan Wuensche

In circuit design, wrong connectivity may cause undesired leakage paths that may result in current hotspots. These current hotspots can be quickly identified with Spectre’s dynamic design checks. This blog describes how to use the Spectre design checks to identify the root cause of leakage path current hotspots.
- 28 Mar 2021
Digital Design: Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff

Sarita Sharma

The beauty of Pegasus is that it doesn’t only work excellently in standalone mode but also seamlessly integrates with other tools such as the industry-standard Virtuoso custom/analog platform and enables users to complete advanced-node DRC in h...
- 26 Mar 2021
Breakfast Bytes: Stopping Online Fraud

Paul McLellan

I attended a webcast on Anti-Fraud organized by the RSA Conference in the leadup to the conference itself. It will be virtual, of course, and it will be held from May 17 to 20. If any aspect of your job involves security, or you are just interested, ...
- 26 Mar 2021
Analog/Custom Design: Virtuoso Video Diary: Tabular Graph in Virtuoso Visualization and Analysis XL

YaswanthSai D

Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis XL to analyze waveform data. Click here to know more.
- 25 Mar 2021
Academic Network: Cadence on YouTube

Anton Klotz

One of the most popular platforms of the whole Internet is undeniably YouTube; this is a place where every user can upload and watch videos about all topics that mankind has ever defined as interesting or worthwhile show...
- 25 Mar 2021
Breakfast Bytes: Best of CadenceLIVE 2020: Hyperscale Data Centers

Paul McLellan

There is something in philosophy known as the Sorites paradox. If you have a heap of sand, and you remove a grain, is it still a heap? Well, sure. So, remove another grain. It's still a heap. But if you keep removing sand, do...
- 25 Mar 2021
Life at Cadence: Women’s History Month Reflections with Alessandra Costa

Mary Kasik

Women’s History Month looks at the achievements women have made over the years. It is a time to honor the women in our lives who have made a difference and encourage the continued advancement of gender equality. At Cadence, we want to recogniz...
- 24 Mar 2021
RF /マイクロ波設計: [4月9日開催] CadenceTECHTALK 5G/6Gのシステム解析を加速する AWRと3D Glass Solutions

RF Design Japan

　ケイデンスでは、これまで定期的にオンラインセミナーを開催し、高周波設計向けソリューションを紹介して参りました。今回は、5Gや今後の6Gのような無線通信に向けた取り組みとして独自の加工技術により注目されている3D Glass Solutions(３DGS)社の技術を紹介させて頂くWebinarを企画いたしました。３DGS社が用意する設計キット(PDK)は弊社のCadence AWR設計環境向けに用意されており、お客様の設計を効率化する弊社のユニークで強力な機能がふんだんに盛り込まれています。 ...
- 24 Mar 2021
Breakfast Bytes: National Security Commission on Artificial Intelligence

Paul McLellan

The (U.S.) National Security Commission on Artificial Intelligence recently published its final report. The report is 756 pages long, so I am not going to claim that I've read it all. I read the introduction and some of the conclusion, and the ch...
- 24 Mar 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: EMX — 業界をリードするRFIC用電磁界ソルバー

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 23 Mar 2021
Verification: TileLink: Chip-Scale Cache-Coherent Interconnect Protocol

RashmiMathanKumar

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the industry.

TileLink is a free and open standard chip-scale interconnect protocol designed for RISC-V processors and beyond (could be used with other ISAs as well). It’s a fast scalable SoC communication protocol designed to connect multiprocessors…
- 23 Mar 2021
System, PCB, & Package Design : IC Packagers: How to Quickly Push Design Connectivity across a Design

avijeet

The task of IC/package co-design causes multiple challenges during the design cycle and one of them is to update the netlist of co-design die or BGA in the middle of the design cycle. The current process of updating connectivity provides no flexibili...
- 23 Mar 2021
Analog/Custom Design: Virtuoso ICADVM20.1 ISR17 and IC6.1.8 ISR17 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for download.
- 23 Mar 2021
Spotlight Taiwan: Sigrity X 2021 盛裝登場!

candyyu

原文出處: Announcing Sigrity X作者: Paul McLellan 在EDA領域中運用了許多不同的運算軟體。然而EDA產業所面臨的挑戰在於，設計團隊總需要採目前處理器來設計及創建下一代的SoC。然而，在1990年代和2000年代，微處理器公司（主要是英特爾，但也包括Sun、HP、Digital等）將處理器的性能每年提高約50％來解決這個問題，部分是因為摩爾定律 - 在沒有產生電源問題的同時，提高矽晶片的性能；還有部分來自於處理器的架構的提升，以更聰明的方法來執行...
- 23 Mar 2021
Breakfast Bytes: Verilog HDL and Its Ancestors and Descendants

Paul McLellan

Most conferences take place annually, or in some cases every two years. The History of Programming Languages (HOPL) is held more like once every fifteen years. The first three were held in 1978, 1993, and 2007. The fourth was going to be held last ye...
- 23 Mar 2021
Verification: Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage

Neelabh

All the workings of USB4 protocol are primarily about how to transfer the native protocol data through tunneling from their originating points to respective destinations. One may verify thoroughly the core layers, like logical layer and transport layer, of a USB4 design. But that is only half the job done.

The next challenge comes up at verifying the tunneling of each native protocol, which are USB3, PCIe, and DisplayPort…
- 22 Mar 2021
Digital Design: iSpatial: Next-Generation Common Physical Optimization Flow

Neha Joshi

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion all lead to a higher netlist requirement. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optim...
- 22 Mar 2021
Breakfast Bytes: DeepChip Best of 2020: Xcelium ML

Paul McLellan

Recently, I wrote about #2a on Cooley's Best of 2020 list, which was Cadence's vManager. See my post DeepChip Best of 2020: vManager. Number #2b on John's list is Xcelium ML. As I said in the earlier post, Paul Cunningham likes to tal...
- 22 Mar 2021
Breakfast Bytes: Sunday Brunch Video for 21st March 2021

Paul McLellan

https://youtu.be/i96zZHBFnTQ Made in my kitchen (camera Ziyue Zhang) Monday: The History of PCIe: Getting to Version 6 Tuesday: Announcing Sigrity X Wednesday: DeepChip Best of 2020: vManager Thursday: Offtopic: Man Wife Lung Slices (夫妻肺片) Friday: Ca...
- 21 Mar 2021
System, PCB, & Package Design : BoardSurfers: How to Create and Remove External DRCs using SKILL in PCB Editor

Monika

Design rules checks (DRC) determines whether your layout design complies with design constraints and highlights any violations. Performing DRC is an essential step of PCB development signoff before you generate manufacturing files. With increasing mi...
- 18 Mar 2021
Breakfast Bytes: Offtopic: Man Wife Lung Slices (夫妻肺片)

Paul McLellan

Tomorrow is a Cadence global holiday. That's what it sounds like. Breakfast Bytes will not appear, and as is now traditional, the day before any break I go off-topic. The Friday before Martin Luther King Jr Day, I wrote about cooking spatchcock c...
- 18 Mar 2021
PCB解析／ICパッケージ解析: Sigrity / Systems Analysis 2021.1 リリース(2021年2月) - 新機能ハイライト

SPB Japan

SIGRITY から SIGRITY/SYSANLSへのリネーム SIGRITYリリースは、これからはSIGERITY/SYSANLSという名称で呼ばれることになります。SYSANLSはSystem Analysisを意味しており、Clarity 3D SolverならびにCelsius Thermal Solverを包含します。Systems Analysis製品はSigrityツールを補完するもので、システム全体にフォーカスしています。熱、EMI、RF、および抽出シミュレーションには、EC...
- 18 Mar 2021
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre XDP-HB (Distributed HB) のご紹介

Custom IC Japan

SPECTER 20.1.ISR4以降のリリースでは、新しいSpectre® X-RFシミュレーションテクノロジーの一部としてSpectre XDP-HBがリリースされました。Spectre XDP-HBは、高度に分散されたマルチマシン、マルチコアシミュレーションテクノロジーを使用して、HBおよびHB小信号解析を実行します。このブログでは、Spectre XDP-HBテクノロジーを紹介します。 Spectre XDP-HB の概要 Spectre XDP-HBは、大規模なメモリ使用、また...
- 17 Mar 2021
RF /マイクロ波設計: μWaveRiders:RF /マイクロ波の学生様向けCadence AWRの大学プログラム

RF Design Japan

　Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るために、Subscrib...
- 17 Mar 2021

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