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Verification: TileLink: Chip-Scale Cache-Coherent Interconnect Protocol

RashmiMathanKumar

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the industry.

TileLink is a free and open standard chip-scale interconnect protocol designed for RISC-V processors and beyond (could be used with other ISAs as well). It’s a fast scalable SoC communication protocol designed to connect multiprocessors…
- 23 Mar 2021
System, PCB, & Package Design : IC Packagers: How to Quickly Push Design Connectivity across a Design

avijeet

The task of IC/package co-design causes multiple challenges during the design cycle and one of them is to update the netlist of co-design die or BGA in the middle of the design cycle. The current process of updating connectivity provides no flexibili...
- 23 Mar 2021
Analog/Custom Design: Virtuoso ICADVM20.1 ISR17 and IC6.1.8 ISR17 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for download.
- 23 Mar 2021
Spotlight Taiwan: Sigrity X 2021 盛裝登場!

candyyu

原文出處: Announcing Sigrity X作者: Paul McLellan 在EDA領域中運用了許多不同的運算軟體。然而EDA產業所面臨的挑戰在於，設計團隊總需要採目前處理器來設計及創建下一代的SoC。然而，在1990年代和2000年代，微處理器公司（主要是英特爾，但也包括Sun、HP、Digital等）將處理器的性能每年提高約50％來解決這個問題，部分是因為摩爾定律 - 在沒有產生電源問題的同時，提高矽晶片的性能；還有部分來自於處理器的架構的提升，以更聰明的方法來執行...
- 23 Mar 2021
Breakfast Bytes: Verilog HDL and Its Ancestors and Descendants

Paul McLellan

Most conferences take place annually, or in some cases every two years. The History of Programming Languages (HOPL) is held more like once every fifteen years. The first three were held in 1978, 1993, and 2007. The fourth was going to be held last ye...
- 23 Mar 2021
Verification: Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage

Neelabh

All the workings of USB4 protocol are primarily about how to transfer the native protocol data through tunneling from their originating points to respective destinations. One may verify thoroughly the core layers, like logical layer and transport layer, of a USB4 design. But that is only half the job done.

The next challenge comes up at verifying the tunneling of each native protocol, which are USB3, PCIe, and DisplayPort…
- 22 Mar 2021
Digital Design: iSpatial: Next-Generation Common Physical Optimization Flow

Neha Joshi

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion all lead to a higher netlist requirement. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optim...
- 22 Mar 2021
Breakfast Bytes: DeepChip Best of 2020: Xcelium ML

Paul McLellan

Recently, I wrote about #2a on Cooley's Best of 2020 list, which was Cadence's vManager. See my post DeepChip Best of 2020: vManager. Number #2b on John's list is Xcelium ML. As I said in the earlier post, Paul Cunningham likes to tal...
- 22 Mar 2021
Breakfast Bytes: Sunday Brunch Video for 21st March 2021

Paul McLellan

https://youtu.be/i96zZHBFnTQ Made in my kitchen (camera Ziyue Zhang) Monday: The History of PCIe: Getting to Version 6 Tuesday: Announcing Sigrity X Wednesday: DeepChip Best of 2020: vManager Thursday: Offtopic: Man Wife Lung Slices (夫妻肺片) Friday: Ca...
- 21 Mar 2021
System, PCB, & Package Design : BoardSurfers: How to Create and Remove External DRCs using SKILL in PCB Editor

Monika

Design rules checks (DRC) determines whether your layout design complies with design constraints and highlights any violations. Performing DRC is an essential step of PCB development signoff before you generate manufacturing files. With increasing mi...
- 18 Mar 2021
Breakfast Bytes: Offtopic: Man Wife Lung Slices (夫妻肺片)

Paul McLellan

Tomorrow is a Cadence global holiday. That's what it sounds like. Breakfast Bytes will not appear, and as is now traditional, the day before any break I go off-topic. The Friday before Martin Luther King Jr Day, I wrote about cooking spatchcock c...
- 18 Mar 2021
PCB解析／ICパッケージ解析: Sigrity / Systems Analysis 2021.1 リリース(2021年2月) - 新機能ハイライト

SPB Japan

SIGRITY から SIGRITY/SYSANLSへのリネーム SIGRITYリリースは、これからはSIGERITY/SYSANLSという名称で呼ばれることになります。SYSANLSはSystem Analysisを意味しており、Clarity 3D SolverならびにCelsius Thermal Solverを包含します。Systems Analysis製品はSigrityツールを補完するもので、システム全体にフォーカスしています。熱、EMI、RF、および抽出シミュレーションには、EC...
- 18 Mar 2021
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre XDP-HB (Distributed HB) のご紹介

Custom IC Japan

SPECTER 20.1.ISR4以降のリリースでは、新しいSpectre® X-RFシミュレーションテクノロジーの一部としてSpectre XDP-HBがリリースされました。Spectre XDP-HBは、高度に分散されたマルチマシン、マルチコアシミュレーションテクノロジーを使用して、HBおよびHB小信号解析を実行します。このブログでは、Spectre XDP-HBテクノロジーを紹介します。 Spectre XDP-HB の概要 Spectre XDP-HBは、大規模なメモリ使用、また...
- 17 Mar 2021
RF /マイクロ波設計: μWaveRiders:RF /マイクロ波の学生様向けCadence AWRの大学プログラム

RF Design Japan

　Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るために、Subscrib...
- 17 Mar 2021
RF Engineering: μWaveRiders: Cadence AWR University Program for RF/Microwave Students

TeamAWR

For students in the RF/Microwave area of study, the Cadence AWR Design Environment platform provides a range of tools that are extremely useful for many tasks, ranging from theoretical concept verification to advanced design capabilities covering the entire industry. The AWR academic license bundle includes an impressive list of capabilities via various tools integrated into a single platform.
- 17 Mar 2021
Computational Fluid Dynamics: ETNZ Wins the America's Cup Once Again Using FINE/Marine

Paul McLellan

Once again Emirates Team New Zealand has entered the history books and won the America’s Cup for New Zealand for the fourth time. After four years of planning and development, 170 years of Cup history, the last races of this 36th edi...
- 17 Mar 2021
Breakfast Bytes: DeepChip Best of 2020: vManager

Paul McLellan

We just finished 2020 (and let's hope 2021 is a better year). Every year, John Cooley runs a "best of EDA" survey, in which users vote on the best EDA products. This year, #2a on John's list is Cadence's vManager Verification Management. John announc...
- 17 Mar 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: Virtuoso RF ソリューション — フローの革命が次のレベルへ突入

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 16 Mar 2021
Analog/Custom Design: Virtuoso Meets Maxwell: How to Simulate an RF Block with Passive and Active Devices in EMX Planar 3D Solver?

jgrad

Do you work with RF designs that contain both active and passive devices? Have you been running electromagnetic simulations for those designs by making a copy of the design and removing active devices? So you have not explored the advanced full-cellview extraction feature yet. Read this blog to know more..
- 16 Mar 2021
Breakfast Bytes: Announcing Sigrity X

Paul McLellan

There are many different computational software algorithms used in EDA. One challenge of EDA is that design groups are always creating the next generation of SoCs on the current generation of processors. In the 1990s and 2000s, however, the microproc...
- 16 Mar 2021
RF /マイクロ波設計: AWR製品の技術サポートがCadence Online Supportに移行されました!

RF Design Japan

2021年3月8日以降、AWR製品の技術サポートは標準のケイデンスサポートプロセスに移行されました。このページは、この移行を通じてAWR製品のお客様を支援するトピックのコレクションです。ケイデンスオンラインサポートシステムを紹介するこの短いビデオをご覧ください。Cadence Online Support この変更の詳細は、AWRのナリッジベースのここで確認できます。また、日本語の書類もいくつか用意しました。ケイデンスオンラインシステムに登録する方法。希...
- 16 Mar 2021
定制IC芯片设计 : Virtuoso Meets Maxwell：跨结构电磁提取功能- 简化IC、封装和电路板耦合的任务

jgrad

当您在设计RFICs或RF模块时，如果只分析IC或模块上的电磁行为，那么可能会造成结果缺失。即使IC的电磁行为已达到其规格要求，也很容易将其耦合至模块周边的走线上，从而影响我们的判断。因此，只有IC和模块组合而成的电磁模型才能确保我们的系统按预期运行。通常对于我们说，组装IC 和封装几何形状是非常繁琐且容易出错的。我们必须手动从各个不同的平台调取数据，并且将其组装成3D模型。甚至有时每次设计迭代时，我们还需要手动重复这些步骤。.
- 15 Mar 2021
Breakfast Bytes: The History of PCIe: Getting to Version 6

Paul McLellan

PCIe, or Peripheral Component Interconnect Express which nobody ever says, was an upgrade to the earlier PCI bus. This was developed by Intel and introduced in 1992. It replaced several older, slower buses that had been used in a somewhat ad-hoc fash...
- 15 Mar 2021
Breakfast Bytes: Sunday Brunch Video for 14th March 2021

Paul McLellan

https://youtu.be/bzgotynPvs8 Made at Fry's Electronics in San Jose (camera Ziyue Zhang) Monday: Your Best Buys Are Always at Fry's Tuesday: Let’s Talk About Chiplets, Baby Wednesday: Paul Cunningham's DVCon Keynote: Verification Throu...
- 14 Mar 2021
Academic Network: Expanding Our Network — AWR Academic Partners

Kira Jones

We want to continue highlighting the amazing AWR academic connections! We’ll be covering the relationship with the University of Bristol and their many professor contacts, but specifically Professor Francesco Fornetti. We are also excited to a...
- 12 Mar 2021

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