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Breakfast Bytes: Cadence Wins Texas Instruments' Supplier Excellence Award

Paul McLellan

I attended the online ceremony recently in which Texas Instruments (TI) formally awarded Cadence their Supplier Excellence Award. It is the first time ever that this award has gone to an EDA/IP company. The award itself is a heavy piece of glass...
- 31 Aug 2020
カスタムIC／ミックスシグナル: Virtuosity: トレースの特定

Custom IC Japan

近年、実行する必要があるシミュレーション数が増えることで、プロットの数が膨大となり、各プロットが、どのCadence® Virtuoso® ADE XL、 Virtuoso® ADE Assembler または Virtuoso® ADE Explorer の履歴、テスト、またはコーナーに属しているかを理解するのが困難になっています。こういった問題に対応するために、IC.6.1.8/ICADVM18.1の、Virtuoso® Visualiza...
- 31 Aug 2020
PCB設計／ICパッケージ設計: BoardSurfers: Allegro In-Design Crosstalk Analysis：PCBキャンバスでシグナルインテグリティシミュレーション

SPB Japan

クロストークとは”アグレッサー”ネットから”ビクティム”ネットへの不要な信号の転送であり、PCB設計で生じる可能性のあるシグナルインテグリティ（SI）問題の中でも主要なものの1つです。クロストークを可能な限り低減することは、PCB設計にとって常に重要です。多くの場合、専用ツールを使用したクロストーク解析の実行には、専門知識が求められ、またドライバー／レシーバーモデルの詳細についての理解も必要とされる、時間の掛かる作業となります。 Allegro&r...
- 30 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 30th August 2020

Paul McLellan

https://youtu.be/IwA132i-R80 Made in "an aquarium" Monday: Under the Hood of Xcelium ML Tuesday: Cadence Certified on TSMC N3, Ultralink on N6, and 3DFabric Wednesday: HOT CHIPS Server and Laptop Processors: Intel, AMD, IBM, Marvell Thursday: TS...
- 30 Aug 2020
Breakfast Bytes: TSMC: Specialty Processes and Specialty Packaging

Paul McLellan

Last Monday was the TSMC Technology Summit 2020. Virtual, of course. I covered that in my post TSMC Technology Symposium: All the Processes, All the Fabs. Today it is the turn of specialty processes and advanced package, for which TSMC now uses ...
- 28 Aug 2020
Digital Design: Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 1

AbhaRawat

With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.
- 27 Aug 2020
Analog/Custom Design: Virtuosity: In the Line of Veri-Fire - Episode 5

Team ADE Verifier

Welcome to the fifth episode of the Veri-Fire series. Check out the new questions and answers that we have for you!
- 27 Aug 2020
System, PCB, & Package Design : BoardSurfers: Extending Allegro Layout Capabilities with SKILL

Rachna2018

Why do I need SKILL? The difference between generic departmental store clothing and premium custom tailoring is what the effective use of SKILL scripts can bring to your PCB Layout design world. While our layout applications come loaded with power-packed features...
- 27 Aug 2020
Life at Cadence: Five Pieces of Advice I Wish I’d Known When I Started My Career

Jaswinder

Congratulations to the members of class of 2020 who are newly embarking on a journey into the workforce! This marks an important phase in your lives as you transition from the academic world into the corporate world. In my 32-year long career, I hav...
- 27 Aug 2020
Breakfast Bytes: TSMC Technology Symposium: All the Processes, All the Fabs

Paul McLellan

Last Monday it was the TSMC Technology Symposium, held virtually of course. Today, I'm going to cover a little bit on the opening, but then focus on advanced digital processes (presented by YJ Mill) and manufacturing excellence (presented by YP C...
- 27 Aug 2020
Life at Cadence: The Returnship Journey: Part 3

Ale Costa

Madhu Comandur's Journey Returnship programs are essential in helping professionals restart their careers after an extended break. According to a study by the ManpowerGroup, 84% of millennials—both men and women—say they anticipate &l...
- 26 Aug 2020
Breakfast Bytes: HOT CHIPS Server and Laptop Processors: Intel, AMD, IBM, Marvell

Paul McLellan

At the recent HOT CHIPS, the first day was dedicated to general-purpose processors, and the second day to special-purpose processors. Today, I'm going to take a look at some of the processors presented on the first day. If we look at server chips, th...
- 26 Aug 2020
System, PCB, & Package Design : IC Packagers: Establishing Connectivity Between Die and BGA

Tyler

The BGA component serves the primary role of redistributing the signals from the die it protects to an interface pattern (the BGA’s balls) compatible with the host PCB it mounts on. As a result, many IC package designs are among those who do no...
- 25 Aug 2020
Analog/Custom Design: Virtuosity: Do Rulers Rule Your Layout Designs?

KomalJohar

You can now use the segment mode, Auto, while creating the ruler. This feature lets you create multiple rulers in just two clicks.
- 25 Aug 2020
Breakfast Bytes: Cadence Certified on TSMC N3, Ultralink on N6, and 3DFabric

Paul McLellan

Yesterday was it TSMC Technology Symposium. Normally this would have been held face-to-face in April but, like everything else, it has gone virtual. Today, it is the OIP Ecosystem Forum. As usual, Cadence is making some TSMC-related announcement...
- 25 Aug 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Unified Libraries — Making Way For Cross-Platform Flows

deeptig

Heterogeneous integration of components using different process technologies can appear to be magic! It mitigates the high cost of homogeneous system-on-chip (SOC) integration by allowing designers to combine proven designs, which use older nodes, on substrates by using newer process technologies. Traditional outsourced assembly and test (OSAT) vendors and IC vendors are competing to provide integration methodologies…
- 24 Aug 2020
Breakfast Bytes: Under the Hood of Xcelium ML

Paul McLellan

At the recent CadenceLIVE Americas, Yosinori (Yoshi) Watanabe presented what he titled Accelerate Regression Performance with Machine Learning. He had to give it such an anodyne title since it appeared in the agenda before the product had b...
- 24 Aug 2020
Breakfast Bytes: Sunday Brunch Video for 23rd August 2020

Paul McLellan

https://youtu.be/LIKlevqCB-U Made in front of my TV (camera Carey Guo) Monday: Alberto's Keynote: Cadence and Academia Tuesday: Climbing Annapurna to the Clouds Wednesday: Thermal Analysis of Protium X1 Thursday: HOT CHIPS: Scaling out Deep ...
- 23 Aug 2020
PCB、IC封装：设计与仿真分析: Sigrity Aurora：融合Allegro用户体验与Sigrity强大功能，为工程师提供设计同步分析

Sigrity

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “Sigrity Aurora: In-Design Analysis“。 space Cadence最新发布的Sigrity Aurora工具将Allegro®用户体验与Sigrity引擎的强大功能相结合。借助这项新工具，设计团队能够在Allegro单一环境中实现：初步探索、设计、仿真分析、最终验证和签...
- 22 Aug 2020
Academic Network: Custom IC, Analog, and RF Design Training Deep Dive: Part 4

Kira Jones

Welcome to the fourth and final part of the Custom IC, Analog, and RF Design Online Training deep dive blog series. In parts one, two, and three, we’ve covered a variety of tools including Virtuoso, Spectre Simulation, Xcelium mixed-signal opti...
- 21 Aug 2020
Digital Design: Pegasus Verification System Product Page is Live!!!

Sarita Sharma

We are excited to share that PegasusTM Verification System Product page is now live on Cadence Online Support site. This page is the one-stop destination where you will get all PegasusTM related information. Here is the glimpse of the page: Let&rsqu...
- 21 Aug 2020
Breakfast Bytes: Anirudh's Keynote: A New Product...and an Acquisition

Paul McLellan

Anirudh Devgan, Cadence's President, gave the keynote to open the second day of CadenceLIVE Americas. He titled it Computational Software for Intelligent System Design. To avoid duplication, in this blog post I'm not going to talk about two&n...
- 21 Aug 2020
System, PCB, & Package Design : 2019 HF2 Release for Clarity, Celsius, and Sigrity Tools Now Available

SigrityReleaseTeam

The 2019 HF2 production release for Clarity, Celsius, and Sigrity tools is now available for download at Cadence Downloads. SIGRITY2019 HF2 For information about supported platforms, compatibility with other Cadence tools, and details of key...
- 20 Aug 2020
Analog/Custom Design: Virtuosity: What's New in Run Plan - Part IV

Yagya Mishra

Click here to view our latest blog in the What's New in Run Plan blog series that discusses the enhancements added to the Run Plan assistant across different Virtuoso ADE Assembler IC6.1.8/ICADVM18.1 ISR releases.
- 20 Aug 2020
Breakfast Bytes: HOT CHIPS: Scaling out Deep Learning Training

Paul McLellan

The annual HOT CHIPS conference took place on August 17-18. Of course, it was virtual. As always, on the Sunday before there were two half-day tutorials. In the morning, it was on scaling deep learning training. In this context, "scaling" m...
- 20 Aug 2020

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