Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Life at Cadence: A Day in the Life: HR Intern Edition

Michelle Hoffmann

Written by Alisha Jain Every day as a Cadence intern brings something new – whether it’s a project you’ve never tackled before or surprise conchas in the kitchen (both equally exciting). I started my morning around 8:30am with...
- 18 Sep 2025
Physical Systems Simulation (CAE): How Multiphysics Is Transforming Product Design

Cadence MSC Software

This page was originally published as a part of Hexagon's Design and Engineering blog. Hexagon Design and Engineering is now a part of Cadence. Product design, as a discipline, has its roots in the Industrial Revolution of the 18th and 19th cent...
- 17 Sep 2025
Corporate News: Building a Future Beyond Boundaries with Honda and Cadence

Corporate

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration with Honda's research efforts emphasizes our commitment to advancing electronic design automation (EDA). We are honored to have Dr. Anirudh Devgan, o...
- 17 Sep 2025
SoC and IP: Cadence Powers AI Infra Summit '25: Memory, Interconnect, and Interface Focus

Joe C

AI is driving a new semiconductor renaissance—it's no longer just a workload, but the defining force behind a new era of semiconductor innovation. Cadence Fellow Charles Alpert echoed this message in his keynote, "Design for AI and AI for Design," offering insights into how AI is reshaping infrastructure and accelerating innovation. His talk set the tone for the AI Infra Summit 2025, paving the way for the Cadence Silicon…
- 16 Sep 2025
Digital Design: RTL-to-GDSII Back-End Flow: Navigating from Synthesis to Timing Signoff

P Saisrinivas

Are you interested in learning the key steps to designing a physical layout from synthesis to signoff? Do you want to know the latest AI features in the RTL2GDSII back-end flow?

Join Cadence Training and Sai Srinivas P, Lead Education Application Engineer, for this free technical training webinar and get insights from industry experts:
RTL-to-GDSII Back-End Flow: Navigating from Synthesis to Timing Signoff

In this webinar…
- 16 Sep 2025
Corporate News: The Birth of the Integrated Circuit

Reela Samuel

On September 12, 1958, in a modest lab in Dallas, Texas, the seeds of a digital revolution were sown. Jack Kilby, an inventive engineer at Texas Instruments, demonstrated the world's first integrated circuit (IC). It didn’t look ...
- 12 Sep 2025
System, PCB, & Package Design : Alphawave Designs High-Quality, Complex Chips Quickly with Clarity 3D Solver

MSATeam

Alphawave Semi is a global leader in high-speed connectivity and compute silicon for customers in AI, data centers, 5G wireless infrastructure, data networking, autonomous vehicles, and storage. Faced with the exponential growth of data, the company’s leading-edge technology enables data to travel faster and more reliably using less power.

In this two-minute Designed with Cadence (DWC) video, Daniel Lambalot, senior…
- 11 Sep 2025
Analog/Custom Design: Virtuoso Studio: Schematic Syntax for Hierarchical Nodes and Buses in DeepProbe

Sai Darshan S N

In the ever-evolving world of analog design, efficiency and clarity are key. With the latest enhancements in analogLib's DeepProbe instance, designers can now leverage schematic syntax and bus format support to streamline their debugging and analysis workflows. This blog explores how these features simplify the design process and improve productivity.
Using Schematic Syntax for Hierarchical Nodes
One of the standout…
- 11 Sep 2025
Physical Systems Simulation (CAE): Designing Passengers’ In-Flight Experience

Cadence MSC Software

This page was originally published as a part of Hexagon's Design and Engineering blog. Hexagon Design and Engineering is now a part of Cadence. Many airlines compete on the basis of the in-flight experiences they offer, whether these are extens...
- 11 Sep 2025
Corporate News: VoxelSensors: Enhancing AI Agents Through Unique Perception Systems with Cadence

Tanushri Shah

AI agents are rapidly heading towards offering us personal assistance in our daily lives. To achieve this, the assistants must anticipate the user’s needs and the environment, and be able to process the context. For example, AI agents on a smar...
- 11 Sep 2025
Physical Systems Simulation (CAE): Real-Time Design and Feedback of 3D-Printed Orthopaedic Insoles

Cadence MSC Software

This page was originally published as a part of Hexagon's Design and Engineering blog. Hexagon Design and Engineering is now a part of Cadence. Back pain, foot and lower limb problems, and overpronation, orthopaedic insoles improve and correct ...
- 10 Sep 2025
SoC and IP: Design for Reliability: Midas Safety Platform

Atreya

In today’s safety-critical applications—automotive, aerospace, industrial automation—reliability modeling is not just a best practice, it’s a necessity. One of the most known methodologies for predicting failure rates in integ...
- 10 Sep 2025
Digital Design: Transforming Equivalence Checking with Conformal AI Studio

Atreya

From Manual Debugging to AI-Powered Verification Imagine you're a verification engineer working on a complex SoC design. You've just completed synthesis and are running equivalence checks between your RTL and gate-level netlist. Suddenly, the...
- 8 Sep 2025
Digital Design: From Concept to Cool: Optimizing Low-Power Design with Genus Synthesis Solution

Neha Joshi

Join Cadence Training and Education Application Engineer Architect, Neha Joshi, for this free technical Training Webinar, which will offer a detailed overview of low-power design strategies.

Low-power synthesis isn’t just an IC design flow box to be checked; it's a foundational step and a strategic necessity.

As modern SoCs become more power-sensitive, early power optimization at the synthesis stage becomes…
- 8 Sep 2025
Analog/Custom Design: The Cadence SKILL Language: Where Coding Blends with Chip Design

Vishnu Teja S

Imagine you're working on a critical design project, and you need a coffee break. You can use SKILL to automate the process of saving your work, closing your design, and even ordering a coffee (okay, maybe not that last one, but a designer can dream, right?).
- 8 Sep 2025
Digital Design: Training Insight - Gateway to Smarter Diagnostics with Modus DFT Software

KShubham

In the rapidly evolving landscape of digital semiconductor design and testing, the ability to accurately diagnose manufacturing defects is critical to ensuring product reliability and optimizing yield. Cadence's Diagnostics with Modus DFT Software Solution training offers a structured and comprehensive approach to fault analysis using advanced design-for-test (DFT) methodologies. This course equips engineers and test…
- 5 Sep 2025
RF Engineering: Efficiently Defining the Fundamental, 2nd and 3rd Harmonics Load Impedances

StandingWaves

Defining the 2nd and 3rd harmonics load impedances of an RF/microwave transistor in non-linear operation is a strongly determining factor not only for the synthesis of the output matching but also for the simulation of load-pull power and efficiency ...
- 4 Sep 2025
The India Circuit: Story of Leela Raghavan - Cadence Scholarship Program

Asim Khan

Leela’s story unfolded in a corner of Bangalore—one of quiet strength, profound loss, and an unwavering commitment to rising above life’s challenges. Born into a low-income family, Leela had lived in Thayimane Children's Home, B...
- 4 Sep 2025
Verification: High-Bandwidth Memory Evolution from First-Generation HBM to the Latest HBM4

Shyam Sharma

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the artificial intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like data centers, autonomous driving systems, servers, and cloud computing, just to mention a few domains where bandwidth and performance are key requirements.
HBM History
HBM started as…
- 3 Sep 2025
Digital Design: Race to First-Pass RTL: Improve PPA Targets Using Stratus HLS

Prashanth Adek

Traditional RTL design methodologies often fall short in the race to deliver faster, more efficient, and power-optimized hardware. They are time-consuming, error-prone, and rigid in architectural exploration. Stratus High-Level Synthesis (HLS) is a p...
- 3 Sep 2025
Computational Fluid Dynamics: Sailing Through the Waves of Competitive Racing with Fine Marine

Veena Parthan

Fine Marine's CFD tools enhance performance and efficiency in marine racing design, highlighting how these technologies enable precise analysis and validation of critical fluid dynamics phenomena.
- 2 Sep 2025
SoC and IP: Rethinking AI Infrastructure: The Rise of PCIe Switches

Vanessa Do

Boring? Think Again. PCIe Switches Are the Hidden Power Behind AI When thinking of AI, images of futuristic robots or self-driving cars may come to mind. What might not come to mind are the unsung hardware component heroes that are quietly enabling s...
- 2 Sep 2025
Corporate News: CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

Reela Samuel

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence of over 2,500 visionaries from electronics and AI. Engineers, technology enthusiasts, and industry leaders came together for a day dedicated to pioneering advancem...
- 2 Sep 2025
Verification: Verification of PCIe's TDISP for Device Interface Security

Jasmine Makhija

The TEE Device Interface Security Protocol (TDISP) is a critical component in ensuring the Interface security of devices operating within a Trusted Execution Environment (TEE). It gives a set of rules designed to prevent and mitigate security threats in devices managed by a Trusted Computing Base (TCB). The TCB, comprising software, hardware, and firmware, enforces these security rules to ensure system integrity. Acting…
- 1 Sep 2025
Physical Systems Simulation (CAE): Simulating the Effect of Extreme Conditions on Athletes’ Performance

Cadence MSC Software

This page was originally published as a part of Hexagon's Design and Engineering blog. Hexagon Design and Engineering is now a part of Cadence. What’s the biggest challenge facing high performance athletes this year at the Tokyo games? Fo...
- 1 Sep 2025

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.