• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Community Forums
  3. Cadence Community
Cadence Community
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Search
  • User
Find Other Members ►
Subscriptions
Get email delivery of the Cadence blog (individual posts).
  • Twitter
  • Facebook
  • LinkedIn
  • Google+

Community


Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

  • spiral_inductor_with_shield

    System, PCB, & Package Design : BoardSurfers: Training Insights: Learn RF Design with Allegro X RF PCB Course

    ACat299612
    ACat299612
    The Allegro®︎ X RF PCB course offers a practical, one-day training for engineers to master RF design using Cadence and ADS tools. Learn to integrate RF and digital workflows, optimize layouts, and simulate designs for high-performance applications like 5G modules. Gain certification and boost your professional credibility in the fast-growing RF domain.
    • 31 Aug 2025
  • Join Cadence Community Super User Program

    System, PCB, & Package Design : Join Cadence Community Super User Program

    Renu Vibha
    Renu Vibha
    Join the Community Super User Program to share expertise, inspire peers, and grow professionally through collaboration and recognition.
    • 31 Aug 2025
  • ICSense Designs ASICs for Next-Generation Medical Implants

    Corporate News: ICSense Designs ASICs for Next-Generation Medical Implants

    Tanushri Shah
    Tanushri Shah
    ICsense is a leading supplier of application-specific integrated circuits (ASICs) that specializes in developing and supplying microchips for the next generation of electric vehicles, medical implants, and wearables. However, developing chips for med...
    • 28 Aug 2025
  • Virtuoso Studio IC25.1 ISR1 Now Available

    Analog/Custom Design: Virtuoso Studio IC25.1 ISR1 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    Virtuoso Studio IC25.1 ISR1 production release is now available for download.
    • 27 Aug 2025
  • FMS 25

    SoC and IP: Cadence Drives Next-Gen Memory and Connectivity at FMS 2025

    Vanessa Do
    Vanessa Do
    As AI data centers continue to scale up and out to accommodate increasingly compute-intensive workloads, ensuring memory interfaces and high-speed interconnects are architected for fast and efficient data movement has never been more critical. Cadenc...
    • 27 Aug 2025
  • Enhancing RTL Power Efficiency with xReplay, FlashReplay, and Clock Gating

    Digital Design: Enhancing RTL Power Efficiency with xReplay, FlashReplay, and Clock Gating

    Udaya Shankar
    Udaya Shankar

    Innovative Solutions for Power-Efficient RTL Design and Technology

    As semiconductor designs scale in complexity and power budgets tighten, early and accurate power analysis becomes critical. Simulation and power reduction are fundamental aspects of modern technology development. Cadence's Joules RTL Power Solution offers a comprehensive suite of tools to analyze and reduce power at the RTL level.

    RTL-level power analysis…

    • 26 Aug 2025
  • An Overview of CXL Mode Alternate Protocol Negotiation

    Verification: An Overview of CXL Mode Alternate Protocol Negotiation

    GuoYu1017
    GuoYu1017

    The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers.

    One of the most common alternate protocols is the Compute Express Link (CXL…

    • 25 Aug 2025
  • 3D-ICs in the Automotive Market: Breaking Barriers with AI-Driven EDA Tools

    Corporate News: 3D-ICs in the Automotive Market: Breaking Barriers with AI-Driven EDA Tools

    Reela Samuel
    Reela Samuel

    The automotive industry is experiencing a significant transformation as it adopts innovations like autonomous driving technologies and ultra-connected ecosystems. At the core of this change is a rising demand for compact, high-performance semiconductor solutions that can handle the increasing complexity of modern vehicle architecture. One promising development is three-dimensional integrated circuits (3D-ICs), an innovative…

    • 25 Aug 2025
  • Restoring Nature, One Vine at a Time

    Life at Cadence: Restoring Nature, One Vine at a Time

    Yesenia Carrillo
    Yesenia Carrillo
    Written by Shrini Farrahi A dedicated team of 30 Cadence volunteers recently came together at the Fells Reservoir in Massachusetts for an environmental stewardship event focused on removing invasive vines. Spending the morning at the Fells Reservoir...
    • 25 Aug 2025
  • Case Study: How to Sign Off Your UCIe Interface

    System, PCB, & Package Design : Case Study: How to Sign Off Your UCIe Interface

    MSATeam
    MSATeam

    As 3D heterogeneous integration (3DHI) systems increase in complexity, the importance of the Universal Chiplet Interconnect Express (UCIe) standard is becoming critical to the future of advanced packaging and semiconductor system designs that support AI and high-power computing (HPC) applications.

    A Cadence webinar featuring Sigrity Signal and Power Integrity offers a comprehensive guide for developing a functional UCIe…

    • 25 Aug 2025
  • Realtime CFD: AI/ML and Operational CFD Digital Twins

    Physical Systems Simulation (CAE): Realtime CFD: AI/ML and Operational CFD Digital Twins

    Cadence MSC Software
    Cadence MSC Software
    This page was originally published as a part of Hexagon's Design and Engineering blog. Hexagon Design and Engineering is now a part of Cadence. Very rarely in one’s career does something happen which is simultaneously a paradigm shift and ...
    • 24 Aug 2025
  • MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

    Corporate News: MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

    Corporate
    Corporate
    Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students f...
    • 21 Aug 2025
  • Power Tradeoffs for Chiplets: What Designers Need to Know

    Digital Design: Power Tradeoffs for Chiplets: What Designers Need to Know

    NaomiM
    NaomiM

    The rise of chiplets in advanced system design presents opportunities as well as challenges, particularly in managing power tradeoffs. Unlike traditional system-on-chip (SoC) designs, chiplets involve complex power delivery due to their multi-die structure.

    Read more to learn about power tradeoffs for chiplets and how you can go from managing early-stage power models to ensuring power integrity across interconnected dies…

    • 19 Aug 2025
  • Unlocking Breakthroughs with Accelerated Compute

    Corporate News: Unlocking Breakthroughs with Accelerated Compute

    Reela Samuel
    Reela Samuel
    The future of system and electronic design is here—and it’s unprecedentedly fast. Yet, this rapid evolution is accompanied by significant challenges for the semiconductor industry. Increasing design complexity, shorter time-to-market win...
    • 18 Aug 2025
  • Evolution of CXL PBR Switch in the CXL Fabric

    Verification: Evolution of CXL PBR Switch in the CXL Fabric

    Satish Kumar C
    Satish Kumar C
    Compute Express Link (CXL) is a transformative technology that significantly improves memory access performance. As technology continues to advance, so do the ways we connect and manage and access memory in our computing systems, there is a Port-Base...
    • 18 Aug 2025
  • Shaping the Future Through Experience

    Life at Cadence: Shaping the Future Through Experience

    Yesenia Carrillo
    Yesenia Carrillo
    This summer, Cadence hosted five interns in partnership with Break Through Tech at our San Jose headquarters. Over the course of three weeks, a cohort of bright undergraduate students from San José State University (SJSU) stepped into our offi...
    • 15 Aug 2025
  • AI Inference

    SoC and IP: CNNs and Transformers: Decoding the Titans of AI

    SriramK
    SriramK

    In the rapidly advancing field of artificial intelligence, two neural network architectures have become prominent: convolutional neural networks (CNNs) and transformers. Each architecture has brought significant advancements to various domains, ranging from image recognition, video surveillance to natural language processing (NLP), speech recognition and generation, multimodal AI and more. This article aims to compare…

    • 13 Aug 2025
  • From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success

    SoC and IP: From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success

    Joe C
    Joe C

    Data rates are escalating with seemingly no end in sight due to the insatiable demand for more bandwidth to accommodate AI factories and other data-intensive AI/ML, HPC, cloud, and data center applications. As just one example, the new PCI Express (PCIe) 7.0 specification doubles the bandwidth over its predecessor—boasting a raw bit rate of 128.0 GT/s for a maximum bandwidth of 512 GB/s bidirectionally in a 16-lane configuration…

    • 12 Aug 2025
  • Alphawave Semi – Designing High-Speed Connectivity Solutions with Cadence Tools

    Corporate News: Alphawave Semi – Designing High-Speed Connectivity Solutions with Cadence Tools

    Tanushri Shah
    Tanushri Shah
    Alphawave Semi designs high-speed connectivity solutions for customers in high-growth end markets. Its leading-edge technology pushes the boundaries of wired connectivity capabilities, enabling data to travel faster and more reliably while using lowe...
    • 12 Aug 2025
  • Employee Spotlight: Engineering Excellence and Team Spirit at Cadence

    Life at Cadence: Employee Spotlight: Engineering Excellence and Team Spirit at Cadence

    Michelle Hoffmann
    Michelle Hoffmann
    Behind every milestone at Cadence is a team of passionate individuals who bring energy, purpose, and collaboration to everything they do. One of those individuals is Simran Nanda, a Lead Applications Engineer in the Digital and Signoff Business Group...
    • 11 Aug 2025
  • UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC

    Verification: UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC

    Harinee Rathod
    Harinee Rathod

    For ages, Ethernet has been the backbone of networking — starting from simple web browsing to cloud computing, data centers, automobiles, and more. Ethernet has enabled countless innovations, and now, it's expanding to meet the demands of AI and HPC.

    As the world shifts toward these new technologies, new challenges are emerging. These include increased scale, higher bandwidth density, multi-pathing, and fast…

    • 11 Aug 2025
  • 5 Tips to Optimise Design for Additive Manufacturing

    Physical Systems Simulation (CAE): 5 Tips to Optimise Design for Additive Manufacturing

    Cadence MSC Software
    Cadence MSC Software
    This page was originally published as a part of Hexagon's Design and Engineering blog. Hexagon Design and Engineering is now a part of Cadence. Additive manufacturing is a technology that enables unprecedented design freedom. Being very differen...
    • 10 Aug 2025
  • Clock Tree Synthesis (CTS): The Backbone of Physical Design

    Digital Design: Clock Tree Synthesis (CTS): The Backbone of Physical Design

    P Saisrinivas
    P Saisrinivas

    In the intricate world of digital design, timing is everything. At the heart of this precision lies clock tree synthesis (CTS)—a critical step in the physical design flow that ensures clock signals reach all sequential elements with minimal skew and optimal latency. Whether you're a seasoned engineer or a curious learner, understanding CTS is essential for achieving robust, high-performance silicon.

    As chip…

    • 6 Aug 2025
  • EDA Unplugged: The Behind-The-Scenes Bloopers of Chip Design

    Digital Design: EDA Unplugged: The Behind-The-Scenes Bloopers of Chip Design

    Neha Joshi
    Neha Joshi

    Welcome to the binge-worthy series you didn't know you needed—"EDA: Silicon, Security and Shenanigans." Whether you're a chip whisperer or just here for the memes, these videos will take you from sand to silicon with more plot twists than your favorite series—and yes, the transistors have feelings, too (almost).

    Designed for anyone—from engineers to educators—who's ever been fascinated by…

    • 6 Aug 2025
  • Uniting Innovators: CIC 2025 Showcases Cadence’s One Team Culture

    Life at Cadence: Uniting Innovators: CIC 2025 Showcases Cadence’s One Team Culture

    Michelle Hoffmann
    Michelle Hoffmann
    What happens when 500 Cadence employees from 22 countries come together to share their best ideas? CIC 2025 had the answer. The Cadence Innovation Conference (CIC) is a vibrant celebration of our collective spirit of innovation. This June, global emp...
    • 6 Aug 2025
<>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information