Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Verification: SoCs Verification Management, Traceability and Managing Risks in Semiconductor World

Vinod Khera

With the increased complexity in SoC design and bigger teams, manually updating the specifications across all tools is very tedious. The biggest challenge is the lack of collaboration between the systems and teams. Traceability is another important a...
- 21 Feb 2022
System, PCB, & Package Design : (P)SpiceItUp: Sweeping Multiple Parameters to Enhance Performance

mrigashira

Often you want to see the effect of changing multiple parameters on the performance of your design. For example, you might want to know how the gain or bandwidth of a design is affected when you vary multiple components across a range of values...
- 21 Feb 2022
The India Circuit: Join Cadence at VLSID 2022 Next Week!

Vinod Khera

VLSID 2022, the 35th International Conference of VLSI Design and the 21st International Conference on Embedded Systems, is the world's largest platform for semiconductors, VLSI and Embedded Systems, and is coming up in a couple of weeks. The reputed ...
- 21 Feb 2022
Breakfast Bytes: Sunday Brunch Video for 20th February 2022

Paul McLellan

https://youtu.be/jGAKLppD9YE Made in Lumen5 by me Monday: Generic and Open PDKs Tuesday: China, US, Europe: Everybody's Got a CHIPS Act Wednesday: Automotive: CFD, FuSa, Aging, Vision, Light Thursday: Offtopic: Sudoku and Wordle Friday:...
- 20 Feb 2022
Academic Network: Opening a Certified EDA lab at Sofia University in Bulgaria

Anton Klotz

A few months ago, I was contacted by Dobromir Gaydazhiev, director of Design Support team at GlobalFoundries who suggested to open an EDA lab at University of Sofia, to educate new generation of EDA engineers for the GF office in Bulgaria. The Cadenc...
- 18 Feb 2022
Breakfast Bytes: Offtopic: Sudoku and Wordle

Paul McLellan

Tomorrow is a Cadence "global recharge day" and Monday is Presidents' Day in the U.S. So, as always, on the day before a break, I go off-topic. One thing that has happened during the pandemic is that people have turned to online games as a way of ent...
- 17 Feb 2022
Computational Fluid Dynamics: What Battery Energy Density is Required for Long-Distance Electric Aircraft?

Veena Parthan

Birds inspired us to develop aircrafts capable of flight. Before the Wright brothers mastered sustained and controlled heavier-than-air powered flight in 1903, other pioneers in aviation such as Richard Pearse, William Frost, and Gustave Whitehe...
- 16 Feb 2022
Digital Design: Adopting a Faster, More Efficient Path to Multi-Chiplet Design

Vinod Khera

Gone are the days when process shrinking was considered as the primary driver of product innovation and improved system performance. The path most are taking leads to the world of “More than Moore.” Vertical Stacking of heterogeneous chips and chiplets is the name of the game. It will have a significant impact on applications that require ultra-high-performance and low power, such as multi-core CPUs, GPUs…
- 16 Feb 2022
Breakfast Bytes: Automotive: CFD, FuSa, Aging, Vision, Light

Paul McLellan

That's a lot of acronyms and buzzwords! Just in case you don't know them all, they stand for: CFD: Computational Fluid Dynamics FuSa: Functional Safety Aging: Not just getting old, but in the context of automotive it means analyzing transist...
- 16 Feb 2022
System, PCB, & Package Design : BoardSurfers: Installation Know-How: Configuring OrCAD and Allegro Installations on Windows

Himanshu Saxena

Often, you install the Cadence products with default settings and that suffices to work with the tools. However, you might encounter instances when the default settings may not be enough to serve your requirements. For example, when multiple use...
- 15 Feb 2022
Breakfast Bytes: China, US, Europe: Everybody's Got a CHIPS Act

Paul McLellan

I ran across a very interesting report from the Semiconductor Industry Association (SIA) China’s Share of Global Chip Sales Now Surpasses Taiwan’s, Closing in on Europe’s and Japan’s. The global market share by major regions l...
- 15 Feb 2022
Breakfast Bytes: Generic and Open PDKs

Paul McLellan

One challenge that educators and researchers face is that they typically have no access to real PDKs from the foundries, but PDKs are required to do design, even if there is no plan to actually manufacture the design. PDK stands for process design ki...
- 14 Feb 2022
Computational Fluid Dynamics: Simulate Wind Turbine Blade Aerodynamics Using High-Quality Automated Meshing

Veena Parthan

Dr. Galih Bangga, a scientist with a forte in wind energy research, from the Institute of Aerodynamics and Gas Dynamics (IAG) at the University of Stuttgart, Germany, presented a paper where he discusses about the significance of autom...
- 13 Feb 2022
Breakfast Bytes: Sunday Brunch Video for 13th February 2022

Paul McLellan

https://youtu.be/_Rt6kAURffU Made in Rancho San Antonio County Park (camera Carey) Monday: No post Tuesday: The Return of Breakfast Bytes Wednesday: DATE 2022 Now Fully Virtual Thursday: January Update Friday: CadenceLIVE Sil...
- 13 Feb 2022
Breakfast Bytes: January Update

Paul McLellan

I realize that it is February, but I was sick late January and so I never wrote this update post. Intel and RISC-V Intel just announced a $1B plan to fund RISC-V-based startups and to attract new foundry customers. I covered Intel's foundry plans...
- 11 Feb 2022
Learning and Support: Webinar Invitation: Enhance your Design Power with Joules

MJ Cad

Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? What is this Webinar About? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical...
- 11 Feb 2022
Breakfast Bytes: CadenceLIVE Silicon Valley 2022: You Can Be Part of the Event

Paul McLellan

CadenceLIVE Silicon Valley is scheduled for June 8 and 9, and currently it is planned to be in-person at the Santa Clara Convention Center. I will give a full preview nearer the time once the agenda is settled. Call for Abstracts But now it is your c...
- 10 Feb 2022
Computational Fluid Dynamics: Go Zero Emission with Plug-In Buoys for Ships

Veena Parthan

There has been persistent traffic in the American ports with tons of containers stacked like toy bricks, one on top of the other, waiting for that one brick at the bottom to break or fail. Cargo vessels waiting for hours in long queues, releasing ton...
- 10 Feb 2022
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectre 電圧ドメイン・チェック

Custom IC Japan

Spectre®回路シミュレータは、過渡解析やその他の解析を実行することなく、典型的なセットアップや設計上の問題を特定することができる、スタティックまたはトポロジー・チェックの大規模なセットを提供します。このブログでは、スタティック・電圧ドメイン・チェックをレビューします。モチベーションミックスド・シグナル設計の多くは、複数の電源ドメインを持ち、高電圧と低電圧のデバイスを含んでいます。デジタル回路は通常低電圧で動作しますが、アナログ、電源、ドライバ回路は高電圧で動作することがあります...
- 9 Feb 2022
Breakfast Bytes: DATE 2022 Now Fully Virtual

Paul McLellan

As you can tell from the title of my DATE 2022 preview post Save the DATE: Design and Test Europe 2022, Antwerp the original plan was to have at least some of the event in-person in Antwerp, Belgium. That is no longer happening and the event is ...
- 9 Feb 2022
Verification: Optimizing CPU Time, TAT, and Disk Space using Cadence Xcelium Advanced Technologies for DFT Verification

Vinod Khera

Design for Testability (DFT) simulation is crucial to the SOC design process: rapid turnaround time (TAT) allows for faster pattern verification for each netlist release and more iteration cycles during development, while efficient disk space and com...
- 8 Feb 2022
Analog/Custom Design: Virtuoso ICADVM20.1 ISR23 and IC6.1.8 ISR23 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR23 and IC6.1.8 ISR23 production releases are now available for download.
- 8 Feb 2022
Life at Cadence: 4 Ways Computational Software Is Transforming System Design and Hardware Design

Corporate

System and Hardware Design Strides and Challenges Electronics systems are changing at an accelerating pace, with technologies such as hyperscale data centers, smart devices, 5G communications, building and home automation, self-driving cars and heal...
- 8 Feb 2022
Breakfast Bytes: The Return of Breakfast Bytes

Paul McLellan

If you are an avid follower of Breakfast Bytes, and of course, you should be, you'll have noticed it hasn't appeared for a couple of weeks. I got Covid (despite being triple vaxxed). After a couple of days with a fever and a cough, it seemed to be ov...
- 8 Feb 2022
SoC and IP: High-Speed 112G Design and COM Dependencies

Vinod Khera

The design impairments such as SoC packaging, package-to-board impedance mismatch, and crosstalk due to front panel and backplane connector, as well as noise coupling could have a significant impact on the bit error rate (BER) in a production system. mentioned in Such design impairments These impairments have a much bigger impact as we move towards 112G data rate because of smaller UI and lower SNR. By prescribing…
- 7 Feb 2022

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.