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PCB、IC封装：设计与仿真分析: Allegro X——新一代智能系统设计平台

TeamAllegro

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“ Allegro X, the Design Platform for the Next Generation of Intelligent System Design"。 space Cadence在打造大多数软件时都有一个共同的思路：将软件原生地集成在通用数据库上，以避免数据库转换可能造成的信息误差。这就好比当我们想用翻译软件把文字从法...
- 9 Nov 2023
System, PCB, & Package Design : Knowledge Bytes - Interposer Multi-Block Analysis Using Clarity 3D Layout

Jasmine

This post talks about the new Interposer Multi-Block Analysis flow that makes it very easy to import GDS files of any size and complexity into Clarity 3D Layout.
- 8 Nov 2023
Corporate News: When Excitement STEMs from Action

Bahadir

One hot August day in Tempe, Arizona, my wife LeAnn and I were sitting with our younger daughter, Bria, in the pleasant front courtyard of the freshman engineering dorm at Arizona State University, Bria’s new home for that year. LeAnn looked at...
- 7 Nov 2023
SoC and IP: UCIe Interoperability Between Intel and Cadence

SFUNG

Intel and Cadence are collaborating on an initiative to demonstrate interoperability between Intel’s UCIe IP and Cadence’s UCIe IP.

UCIe is the latest emerging open specification defining the interconnect between two die links in a system in package (SiP). UCIe is expected to enable power-efficient and low-latency chiplet solutions as heterogeneous disaggregation of SoCs becomes mainstream to overcome the…
- 7 Nov 2023
Digital Design: How AI-Based Cadence Cerebrus Improves Performance and Reduces Area for TI

Vinod Khera

Microcontrollers (MCUs) have become the backbone of embedded designs and are fueling the design of various applications. Their importance cannot be overstated, as they offer an enormous opportunity for chip manufacturers. It is a fact that the MCU ma...
- 7 Nov 2023
Corporate News: The Secret Life of Chip Engineers!

Reela Samuel

Chip engineers, the unsung heroes of the tech world, lead a secret life at work that's more mysterious than a spy novel. They huddle around schematics like wizards around a cauldron, whispering incantations in the language of transistors. Well, ...
- 6 Nov 2023
Analog/Custom Design: Stacked MOSFETs in Analog Layout

Mark Williams

Below 28nm, maximum device length limitations mean that analog designers often need to connect multiple short length MOSFETs in series to create long channel devices. These series-connected devices are often called stacked MOSFETs or stacked devices. For example, stacking three 1um MOSFETs in series creates an effective device with a channel length of 3um.

Stacked MOSFETs are very common in modern analog design but…
- 3 Nov 2023
Corporate News: Bringing Semiconductor Tapeouts to Engineering Education

Kira Jones

Cadence’s PDK for SkyWater 130nm Open-Source Semiconductor Process Empowers Students and Helps Bridge the Growing Employment Gap As electronics technology continues to advance at an unprecedented pace, the demand for skilled professionals in th...
- 3 Nov 2023
System, PCB, & Package Design : BoardSurfers: Training Insights—New OrCAD X Presto Layout Design Application

AsadMakandar

The OrCAD X Presto next-generation layout design environment within the OrCAD X platform offers a cutting-edge solution for PCB layout design. Its interoperability with the Allegro X PCB Editor ensures compatibility and easy transition of layout designs.

The OrCAD X Presto provides an easy-to-use and standard user interface that allows designers to work faster and more accurately. The informative and interactive panels…
- 3 Nov 2023
Data Center: A Quick Start Guide: Building a Data Center Digital Twin

MarkSeymour

Even if you know a new software solution could help improve your workflow and data center performance, it can still feel quite daunting to begin the implementation process. In our experience, customers have found that the benefits of digital twin so...
- 3 Nov 2023
System, PCB, & Package Design : Cadence OrCAD X and Allegro X 23.1 is Now Available

AllegroReleaseTeam

The OrCAD X and Allegro X 23.1 release is now available at Cadence Downloads. This blog post contains links for accessing this release and describes some of the major changes made and the new features introduced. OrCAD X /Allegro...
- 2 Nov 2023
SoC and IP: Cadence is a Contributing UCIe Consortium Member

SFUNG

This blog was originally posted on uciexpress.org.

The Cadence member spotlight blog is live and can be found here

Meet UCIe Consortium Member Cadence

By: Sue Hung Fung, Principal Product Marketing Manager, Cadence

Can you share a brief introduction to Cadence?

Cadence (Nasdaq: CDNS) is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The…
- 2 Nov 2023
Computational Fluid Dynamics: Don’t Miss the Amazing Ride that is McLaren Racing Fandom!

Steve Brown

Hey there racing enthusiasts! Today I want to take a moment to talk about a partnership that has been making waves in the world of Formula One racing. It's the incredible collaboration between Cadence and McLaren Racing. As a passionate fan of both ...
- 2 Nov 2023
Computational Fluid Dynamics: Cadence CFD Technology Update – Turbomachinery Workflow

Veena Parthan

The Cadence Fidelity Flow for Turbomachinery is a unique toolset that encompasses a complete end-to-end solution: 1D to 3D design, meshing, CFD, and optimization, all in one single environment. Whether you want to improve simulation accuracy or reduce turnaround time for your turbomachinery workflow, Fidelity Flow can do it!
- 2 Nov 2023
Verification: USB4 Version 2.0 – Link Configurations

Neelabh

USB4 Version 2.0 specification was released by the USB Promoter Group earlier this year. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode.

The new version brings with it the possibility of configuring the USB4 link in asymmetric mode or transitioning to it from the symmetric mode.

There are a few changes in the terminologies as well for describing…
- 1 Nov 2023
Data Center: Validate Data Center Cooling Systems Externally Using CFD

MarkSeymour

It’s no secret that data centers are power hungry, so much so that data centers account for 1-1.5% of global electricity use. Investing in advanced cooling technology, such as indirect or direct adiabatic cooling, can reduce the power usage ne...
- 1 Nov 2023
Verification: Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution

Tyler Sherer

Debugging low-power designs is its own unique challenge in the verification field. Between confirming varying requirements across different power domains and the challenges associated with assuring correctly retained chip states through power cycles, specific low-power verification methodologies are required to reach tapeout. Luckily, Verisium Debug has everything you need to make your low-power debugging as simple and…
- 31 Oct 2023
Verification: Be Optimistic About Xcelium's New X-Pessimism App!

Tyler Sherer

In simulation, X-Propagation has been used to track how unknown states or signals move through a design at RTL. These “Xs” can cause areas of a design to malfunction once the design has been synthesized into its corresponding netlist. Despite all the advantages that today’s simulation provides, there are still occasional discrepancies in the simulated design of a netlist, and this is where the question of using the new…
- 31 Oct 2023
Data Center: Validating Data Center Performance Using Cadence Reality DC Design

Veena Parthan

Data centers have become critical for efficiently processing massive data sets and artificial intelligence (AI) workloads. Reducing the data center power consumption and their effective management are highly prioritized by hyperscalers and enterprises globally. For predictive analysis of data center operational design, Cadence DataCenter Design Software is a go-to solution.
- 31 Oct 2023
Artificial Intelligence (AI): How Will EDA Benefit from the AI Revolution? - Part 2

Vinod Khera

I have always relished technology discussions and expert opinions on how technology will unfold and shape the future. In the panel discussion during CadenceLIVE Europe, experts shared their thoughts about the impact of the AI revolution on EDA. They ...
- 30 Oct 2023
RF Engineering: Training Insights New Course: Planar EM Simulation in AWR Microwave Office

John Dunn

New online training course for AXIEM EM Simulator in AWR Microwave Office is available.
- 30 Oct 2023
System, PCB, & Package Design : Sigrity and Systems Analysis 2023.1 HF2 Release Now Available

SigrityReleaseTeam

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2023.1 HF2 release is now available for download at Cadence Downloads. This blog contains important links for accessing this release and introduces some of the main features that you can look forward to.
- 26 Oct 2023
Data Center: Reduce Data Center Over-Provisioning and Stranded Capacity for Sustainability

Hassan Moezzi

In the ever-evolving landscape of data centers, the issue of stranded capacity has become a significant concern for operators. Stranded capacity refers to the underutilization of resources. It is best referred to as the elephant in the data center du...
- 26 Oct 2023
Artificial Intelligence (AI): How Will EDA Benefit from the AI Revolution?

Vinod Khera

With the rise in demands for instant gratification, high performance, and smart everything, we are witnessing how AI inclusion in almost every industry revolutionizes productivity, design, and performance. The EDA (Electronic Design Automation) indus...
- 26 Oct 2023
Verification: Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

Kunal Chhabriya

Verifying compliance during PCIe re timer testing poses challenges. Cadence PCIe Verification IP not only overcomes the above challenges, but far exceeds them by locking accurately on truncated normal compliance pattern, allowing checkers and counters on them, and supports more skew than spec permitted. All this is available by enabling a simple configurable compliance setting provided as part of Application Programming…
- 25 Oct 2023

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