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Digital Design: Training Webinar: IR-Aware ECO Optimization Using Voltus and Tempus Solutions

sakshin

This blog post draws your attention towards an upcoming training webinar "IR-Aware ECO Optimization using Voltus and Tempus Solutions."
- 11 Aug 2023
Computational Fluid Dynamics: Meshing Complex Marine Geometries Has Never Been Easier!

Veena Parthan

The Cadence Fidelity CFD platform offers various meshing technologies for leading or blunt edges, free surfaces, boundary layers, viscous layers, and more. An overview of a few meshing strategies to ease mesh generation for complex marine geometries is explained in this post.
- 11 Aug 2023
Cloud: Designing with Cadence…in the Cloud

SarahAdams

Recogni builds the world’s highest-performing chips that are fully functional for vision inference in autonomous vehicles. Tessolve is developing an ASIC for a very low-power touch-sense controller chip. Damen is an international shipbuilding g...
- 9 Aug 2023
System, PCB, & Package Design : IC Packagers: Transfer of IC Routing Blockage to Allegro X Advanced Package Designer Route Keepout Using Integrity System Planner

Jasmine

A physical implementation designer may want to add a routing blockage on a chip or a package to optimize various aspects, such as signal integrity, power distribution, thermal management, or meeting manufacturing constraints. Typically, for signal in...
- 8 Aug 2023
Artificial Intelligence (AI): Transformative Potential of Generative AI: Alleviating Talent Shortages and Diversifying Chip Design

Reela Samuel

In the previous posts in this series, we read about the transformative power of generative AI (part 1) and handling possible errors and their impact on chip/system design (part 2). Now, in this third post, our esteemed panel discusses whether generat...
- 7 Aug 2023
Artificial Intelligence (AI): Keep Up with the Revolution—AI/ML Fundamentals Training

FormerMember

Want to learn what artificial intelligence and machine learning (AI/ML) are all about and how they apply to electronic design automation and chip design? Whether you are a software engineer trying to understand hardware design or a hardware engineer ...
- 7 Aug 2023
PCB、IC封装：设计与仿真分析: 信号反射和阻抗失配的联系

Sigrity

本文要点• 电路中或传输线上的阻抗失配会产生反射，回到信号源。• 当信号反射时，向末端负载传输的功率就会减少。• 阻抗匹配发挥了一种双重作用，即通过抑制反射使功率传输到负载。每当电磁信号沿着传输线传播时，都有可能从传输线和负载器件之间的接口上反射回来。负载可以是任何东西：另一段传输线、集成电路、天线......任何有明确阻抗的东西都是负载。当阻抗失配时，就会给信号带来灾难性的影响，导致在传输线末端测得振荡响应或阶梯式响应。这种效应从何而来，如何通过阻抗匹配来加以...
- 7 Aug 2023
PCB、IC封装：设计与仿真分析: 如何轻松完成刚柔结合 PCB 弯曲的电磁分析？

Sigrity

对于使用刚柔结合 PCB 的系统，确保功能性、安全性和有效性是重中之重，尤其是用于先进医疗植入物、高精度关键军事设备以及类似受监管机密设备的系统。为此，一定要对它们进行全面详尽的仿真。Footprint 尺寸较小的系统必须具有很高的封装密度，才能容得下各种器件。随着器件密度增加，电磁 (EM) 问题日益突出，降低了电气性能。3D 设计的复杂性使刚柔结合 PCB 的电磁分析成为一种挑战。刚柔结合电路可以弯曲的这一点，使设计人员能够以较低的成本实现多个空间利用率极高的堆叠设计，因此大受欢迎。对于大...
- 7 Aug 2023
PCB、IC封装：设计与仿真分析: 多层 PCB 的热应力分析

Sigrity

本文要点：多层 PCB 有很多优点，但是，多层结构也会给电路板带来热应力问题。热应力分析是一种温度和应力分析方法，用于确定多层 PCB 中的热应力点。热应力分析结果有助于 PCB 设计人员构建可靠、稳健和经过优化的多层 PCB。印刷电路板 (PCB) 存在于所有电子设备中，是确保设备正常运行的核心元件。每块 PCB 上都载有电子设备的一个重要子系统，用于增加设备的功能。因此，电子设备的功能越多，就需要越多的 PCB 来保证正常运行。为了在设备中整合更多的 PCB，并满足电压要求，PC...
- 6 Aug 2023
Digital Design: Keep Up with the Revolution—Cadence Cerebrus Training

FormerMember

Can you imagine specifying your design goals and having a tool intelligently optimize the design completely automated? Sounds like a vision? It’s not.

Cadence Cerebrus is a revolutionary chip optimization solution that allows for faster, smaller, and smarter design of semiconductor chips. It scales and automates digital design, resulting in game-changing power, performance, and area (PPA) and improved engineering…
- 4 Aug 2023
Computational Fluid Dynamics: Cleaning Marine Geometries Has Never Been Easier!

Veena Parthan

Ship designers and naval architects increasingly use computational fluid dynamic (CFD) tools for more accurate solutions, detailed physics, and quicker results. But the mesh generation step in CFD often requires expertise and experience, especially when dealing with complex geometries. For easier meshing, the Fidelity CFD platform has various geometry cleaning tools and features to help streamline mesh generation and…
- 4 Aug 2023
PCB、IC封装：设计与仿真分析: 面向 TSMC InFO 技术的高级自动布线功能

SDA China

本文翻译自Cadence "Breakfast Bytes Blogs"专栏作者Paul McLellan文章"Advanced Auto-Routing for TSMC InFO Technologies"。在2022年底举办的 TSMC OIP 研讨会上，Cadence 资深半导体封装管理总监J ohn Park 先生展示了面向 TSMC InFO 技术的高级自动布线功能。InFO 的全称为“集成式扇出型封装（integra...
- 4 Aug 2023
Analog/Custom Design: More Current Mirrors in Analog Layout

Mark Williams

In my previous blog, (Current Mirrors in Analog Layout) I looked at a few techniques for matching MOSFETs in a typical current mirror. In this post, I will look at matching in multiple leg mirrors and the benefits of inserting dummy devices.

The schematic diagram above is of a typical operational amplifier (opamp), displayed in Pulsic’s Animate Preview design tool. The highlights show various structures in the circuit…
- 3 Aug 2023
カスタムIC／ミックスシグナル: Virtuoso Studio: 正しい意図を持ってコラボレートしよう！

Custom IC Japan

当社の最新AI技術を活用したカスタムデザインソリューションであるVirtuoso Studioは、30年にわたる業界の知識とリーダーシップを活用し、革新的な機能や比類のない生産性を実現する再考されたインフラストラクチャおよびクラシックなデザイン境界を超える新しいレベルの統合プラットホームを提供します。このブログシリーズでは、この最高のアナログ設計ツールがどのように改善され、難しい設計問題に対応できるようになったかを学んでいただきます。テクノロジープロセスノードの進歩に伴い、カスタム設計の複雑...
- 3 Aug 2023
Verification: Best Practices to Achieve the Highest Performance Using Xcelium Logic Simulator – Part 2

Reela Samuel

Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters, switches, and profiling. This post will cover analyzing the profiler report. Auto Performance Analysis Xcelium offers an Auto Performance Analysis u...
- 3 Aug 2023
Corporate News: Cadence and Arm Are Building the Future of Infrastructure

Tanushri Shah

Arm has over 30 years of experience in the semiconductor industry. From fueling the smartphone revolution to enabling the software-defined vehicle, Arm is defining the future of computing, and it’s doing so with the help of Cadence. Arm has b...
- 3 Aug 2023
PCB解析／ICパッケージ解析: System Analysis Knowledge Bytes: DC/DCコンバータを正確にモデル化するためのCelsius PowerDCメソトロジー

SPB Japan

System Analysis Knowledge Bytesブログシリーズでは、Cadence®が提供するシステム解析ツールの機能と可能性について説明しています。このシリーズは、この分野での役立つ機能等に関する学識を提供することに加えて、システム解析に関連する知識と経験を共有するブロガーと専門家の意見を広くお伝えすることを目的としています。従来、IR ドロップ解析用に1つのDC-DC/LDOを2つのポート(SinkとVRM)に分離していました。これら2つのソースは...
- 3 Aug 2023
Computational Fluid Dynamics: On-Demand Webinar - Simulating Fluid-Structure Interaction (FSI) with Fidelity

AnneMarie CFD

Fluid-Structure Interaction (FSI) modeling is a fundamental step in the design process of turbomachinery. Highly variable pressure and temperature gradients affect not only efficiency and performance but also the structural integrity of blades. In this TechTalk, we introduce Fidelity’s FSI simulation capabilities, describe how geometry deformation can be modeled, and explain its effect on the fluid field.
- 1 Aug 2023
Analog/Custom Design: Virtuoso Studio: Device-Level Auto Place and Route — Now a Reality!

Vinod Khera

By Sravasti Nair, Product Engineering Group Director, Cadence. The world of semiconductors is advancing rapidly, as is the demand for analog/ mixed-signal designs. However, such designs have high turnaround times; the gating factor is creating layouts that are both design rule and design intent ...
- 1 Aug 2023
Analog/Custom Design: Spectre Tech Tips: GPU Integration with Analog Circuit Simulation

Moustafa Moham

Spectre X GPU offers new computational capabilities that can transform the way large and complex designs are simulated with the best performance. read more ...
- 31 Jul 2023
Analog/Custom Design: Virtuoso Meets Maxwell: Virtuoso Electromagnetic Solver Assistant -Support for Iterated Instances

Udit Kapoor

In this blog, you will see how to use the “Iterated Instance support” capability in the schematic-driven flow.
- 28 Jul 2023
PCB解析／ICパッケージ解析: MR/AR システム向けPowerTreeによるPDN解析, コリレーションとサインオフ

SPB Japan

Meta社は、今年のDesignConで「MR/AR システム向けPowerTree ベースの PDN解析、コリレーションとサインオフ」に関するセッションを開催しました。Meta社のKundan ChandとGrace Yuがプレゼンテーションを行い、Sigrity AuroraとPowerDCやOptimizePIなどの Power Integrityツールを使用したパワーインテグリティ (PI) 解析について話しました。このプレゼンテーションでは、コンデンサ数を制限する省スペ...
- 27 Jul 2023
カスタムIC／ミックスシグナル: Virtuoso Studio: 最速よりも速く - 次の10年に向けたカスタム・プラットフォーム

Custom IC Japan

当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio は、我々の30年にわたる業界の知識とリーダーシップを活用し、革新的な機能、比類のない生産性を実現する再構築されたインフラストラクチャ、および従来の設計の枠を超えた新しいレベルの統合環境を提供します。このブログシリーズでは、最高のアナログ設計ツールがどのように改良され、困難な設計課題に対応できるようになったかを紹介します。 By Olivier Arnaud, Product Engineering Group ...
- 27 Jul 2023
カスタムIC／ミックスシグナル: Virtuoso Studio IC23.1がリリースされました

Custom IC Japan

Virtuoso Studio IC23.1の製品リリースがCadence Downloadsからダウンロードできるようになりました。サポートされているプラットフォームやその他のリリースの互換性情報については、インストールディレクトリのREADME.txtファイルを参照してください。 IC23.1 以下は、Virtuoso Studio IC23.1リリースのハイライトです： Virtuoso Studio IC23.1 Overview ケイデンスのカスタムIC設計ソリュー...
- 27 Jul 2023
Verification: Understanding PCIe 6.0 Shared Flow Control

mrana

As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms of credits, higher data rate means more credits consumed. Today, as the designs are getting complex, the need to have more credits arises. Hence to address this issue, shared credit pool is introduced in PCIe 6.0.
What Is Shared Flow Control?
As the name applies, this means credit shared between two or more VCs.

Here are the latest updates…
- 26 Jul 2023

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