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Latest Blog Posts

  • Virtuoso ICADVM20.1 ISR33 and IC6.1.8 ISR33 Now Available

    Analog/Custom Design: Virtuoso ICADVM20.1 ISR33 and IC6.1.8 ISR33 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    The ICADVM20.1 ISR33 and IC6.1.8 ISR33 production releases are now available for download.
    • 26 Jul 2023
  • 3D-IC: The Future of Integrated Electronics Is the Future of Electronics Itself

    Digital Design: 3D-IC: The Future of Integrated Electronics Is the Future of Electronics Itself

    P Saisrinivas
    P Saisrinivas

                            

    According to Gordon E. Moore, “The future of integrated electronics is the future of electronics itself.” This means that the advantages of integration will bring rapid change in electronics by integrating more transistors on a chip. Moore's law states that the number of transistors on a microchip doubles roughly every two years, leading to exponential growth in power, performance, and area (PPA), ultimately…

    • 26 Jul 2023
  • Boost Your CFD Workflow Productivity with the Fidelity Python API – Part III

    Computational Fluid Dynamics: Boost Your CFD Workflow Productivity with the Fidelity Python API – Part III

    Veena Parthan
    Veena Parthan
    Welcome back to the third and final part of this blog series! In this blog post, we will explain how to create a project template and automate repetitive tasks in a CFD workflow or automate the entire workflow, with specific examples and the knowledge acquired in executing scripts from Part I and Part II of this blog series.
    • 25 Jul 2023
  • BoardSurfers: Training Insights: Reducing Time to Market with Allegro DesignTrue DFM Checks

    System, PCB, & Package Design : BoardSurfers: Training Insights: Reducing Time to Market with Allegro DesignTrue DFM Checks

    anandd
    anandd
    Allegro DesignTrue DFM rules help you perform fabrication, assembly, and test checks in real-time while designing your boards. You can add Allegro DesignTrue DFM rules to your design workflow and run them in the early stages of the design cycle....
    • 25 Jul 2023
  • Flying High Above the Cloud with Cadence

    Cloud: Flying High Above the Cloud with Cadence

    Reela Samuel
    Reela Samuel
    The semiconductor industry has long been ambivalent about embracing cloud technology for design and verification, expressing several concerns in the process. Foremost among these are the potential security risks, difficulties in cost-effectively tran...
    • 24 Jul 2023
  • Importance of Diversity in Generative AI: Ensuring Ethical and Inclusive Technologies

    Corporate News: Importance of Diversity in Generative AI: Ensuring Ethical and Inclusive Technologies

    Paul Scannell
    Paul Scannell
    Generative AI is an exciting field that has the potential to revolutionize many industries, from entertainment to healthcare. Electronic Design Automation (EDA) plays a critical role in the development of generative AI technologies by enabling the d...
    • 24 Jul 2023
  • EDA’s New Dimension of Design: As Moore’s Law Slows, the Industry Moves to 3D-ICs to Maintain Momentum

    Corporate News: EDA’s New Dimension of Design: As Moore’s Law Slows, the Industry Moves to 3D-ICs to Maintain Momentum

    Paul Scannell
    Paul Scannell
    I’ve been thinking lately about the legacy of Gordon Moore, the late Intel co-founder and author of Moore’s Law, which predicted ongoing progress in scaling would lead to a doubling of transistor density every 18 months. It held true for...
    • 24 Jul 2023
  • Virtuoso Meets Maxwell: Custom Passive Device Authoring - Part 1 (Automatic Marker Shape Generation)

    Analog/Custom Design: Virtuoso Meets Maxwell: Custom Passive Device Authoring - Part 1 (Automatic Marker Shape Generation)

    Claudia Roesch
    Claudia Roesch
    You probably heard about the release of Cadence EMX Designer. This blazing fast layout synthesis tool offers significant productivity gains and creates a lot of interest and excitement at trade shows and conferences like International Microwave Symposium (IMS).
    • 23 Jul 2023
  • Start Your Engines: Debugging Mixed-Signal Partitioning Issues Using the Elaborator

    Analog/Custom Design: Start Your Engines: Debugging Mixed-Signal Partitioning Issues Using the Elaborator

    Rick Sanborn
    Rick Sanborn
    Mixed-signal partitioning issues are a common occurrence in mixed-signal functional verification flows. Read this blog to know more about debugging these issues using the elaborator.
    • 21 Jul 2023
  • CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance

    Verification: CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance

    Tanushri Shah
    Tanushri Shah

    Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The latest on-demand CadenceTECHTALK, Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance, shows how you can accelerate your mixed-signal simulations with real number modeling (RNM) and EEnet in the Xcelium Logic Simulator.

    A slide from the Xcelium webinar titled 'Vision of Xcelium Mixed-Signal App'

    Presented by Shekar Chetput and Raj Mitra of Cadence, this webinar will give you an overview of market…

    • 20 Jul 2023
  • Tessolve Is Reinventing Touch-Sense Controls

    Corporate News: Tessolve Is Reinventing Touch-Sense Controls

    Tanushri Shah
    Tanushri Shah
    Imagine you’re trying to get your way back home in snowy weather, and you’re trying to navigate your way through Google Maps. The only thing is, you’re wearing gloves, so it’s hard to use the touch screen. Tessolve is working...
    • 20 Jul 2023
  • Balancing Analog Layout Parasitics in MOSFET Differential Pairs

    Analog/Custom Design: Balancing Analog Layout Parasitics in MOSFET Differential Pairs

    Mark Williams
    Mark Williams

    Differential amplifiers apply gain not to one input signal but to the difference between two input signals. This means that a differential amplifier naturally eliminates noise or interference that is present in both input signals. Differential amplification also suppresses common mode signals. In other words, a DC offset that is present in both input signals will be removed, and the gain will be applied only to the signal…

    • 19 Jul 2023
  • Unraveling Generative AI Risks in Chip/System Design

    Artificial Intelligence (AI): Unraveling Generative AI Risks in Chip/System Design

    Reela Samuel
    Reela Samuel
    When masterminds discuss ideas, possibilities, and perspectives, their collective intelligence unleashes a creative synergy that can lead to groundbreaking innovations and solutions. The CadenceLIVE Silicon Valley event's Generative AI Panel offered ...
    • 19 Jul 2023
  • Virtuoso Studio: Collaborate with the Right Intentions!

    Analog/Custom Design: Virtuoso Studio: Collaborate with the Right Intentions!

    Vinod Khera
    Vinod Khera
    By Girish Vaidyanathan, Sr. Product Marketing Manager, Cadence Design Systems. The complexity of custom designs has significantly increased with advancements in process technology nodes, resulting in longer product lifetimes and shorter expected failure rates.
    • 18 Jul 2023
  • Women in CFD with Colinda Francke

    Computational Fluid Dynamics: Women in CFD with Colinda Francke

    Veena Parthan
    Veena Parthan
    We are excited to feature Colinda Francke, Senior Product Engineering Manager for the Cadence CFD team, in our July edition of the Women in Computational Fluid Dynamics (CFD) series. Colinda has successfully managed her career in the academic field of computational fluid dynamics (CFD) software and quality management, all while fulfilling her childhood dream of raising a family. In our interview, Colinda shares her career…
    • 18 Jul 2023
  • Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator – Part 1

    Verification: Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator – Part 1

    Reela Samuel
    Reela Samuel
    In a landscape characterized by increasingly intricate designs and rapidly diminishing time-to-market, today’s advanced verticals necessitate innovative strategies that yield exceptional performance enhancements, enabling them to maintain a com...
    • 17 Jul 2023
  • Joules RTL Design Studio: Accelerating Fully Optimized RTL

    Digital Design: Joules RTL Design Studio: Accelerating Fully Optimized RTL

    raquelp
    raquelp

    Cadence announced Joules RTL Design Studio today at CadenceLIVE Japan 2023, a new product that expands upon Cadence’s existing Joules RTL Power Solution. The solution will address all aspects of physical design by adding visibility beyond just power into performance, area, and congestion.

    A colorful chip

    Lack of visibility into early power, performance, area, and congestion (PPAC) metrics is a challenge that has, for the most…

    • 13 Jul 2023
  • Recording Now Available: Intro to Genus iSpatial Synthesis Flow Webinar

    Digital Design: Recording Now Available: Intro to Genus iSpatial Synthesis Flow Webinar

    Neha Joshi
    Neha Joshi

    With advanced-process nodes, a standard cell's physical delay, net delay, and congestion lead to a higher netlist requirement.

    Do you want to tackle congestion and achieve a better PPA for your design?

    If so, it's time to gear up with Cadence Genus iSpatial Synthesis flow with Cadence Training and Sr. Principal Education Application Engineer Neha Joshi in the recorded session of the Training Webinar held in May 2023…

    • 13 Jul 2023
  • DEI@Cadence: Do You Know the Dragon Boat Festival?

    Life at Cadence: DEI@Cadence: Do You Know the Dragon Boat Festival?

    Ceci
    Ceci
    Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you’ll find a community where employees share their perspectives and experiences. By pro...
    • 13 Jul 2023
  • How Do Robots Navigate?

    SoC and IP: How Do Robots Navigate?

    Vinod Khera
    Vinod Khera
    Have you ever been amazed by the graceful movement of robots and self-driving vehicles in unfamiliar surroundings? The latest technological advancements have introduced self-cleaning robots, autonomous vehicles with incredible navigation abilities. T...
    • 13 Jul 2023
  • SPECTRE 23.1 がリリースされました

    カスタムIC/ミックスシグナル: SPECTRE 23.1 がリリースされました

    Custom IC Japan
    Custom IC Japan
    SPECTRE 23.1 リリースは、 Cadence Downloadsからダウンロードできます。サポートされているプラットフォームおよびその他のリリースの互換性情報については、インストール階層にある README.txt ファイルを参照してください。   SPECTRE 23.1   以下は、SPECTRE 23.1リリースで行われた重要なアップデートのリストです。 Using GPU with Spectre X Spectre XがNVIDIAのGPUプラットフォーム...
    • 12 Jul 2023
  • Virtuoso Studio IC23.1 Now Available

    Analog/Custom Design: Virtuoso Studio IC23.1 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    Virtuoso Studio IC23.1 production releases are now available for download.
    • 12 Jul 2023
  • Recogni Is Making AI-Based Vision Inference Chips

    Corporate News: Recogni Is Making AI-Based Vision Inference Chips

    Tanushri Shah
    Tanushri Shah
    Recogni is an AI chip start-up incorporated in 2017 for the automotive market. Like most companies, the pandemic threw a curve at them. After only four months into their design effort, everyone had to go home. Things worked out for the better for Rec...
    • 12 Jul 2023
  • System Analysis Knowledge Bytes: A Step-by-Step Guide to Shorting Nets in Sigrity PowerSI and Other Layout-Based Analysis Tools

    System, PCB, & Package Design : System Analysis Knowledge Bytes: A Step-by-Step Guide to Shorting Nets in Sigrity PowerSI and Other Layout-Based Analysis Tools

    Jasmine
    Jasmine
    The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence®. In addition to providing insight into the useful features and enhancements in this area, this series ...
    • 12 Jul 2023
  • BoardSurfers: Training Insights: Improve Debugging Efficiency Using Procedures In inspectAR-Allegro Flow

    System, PCB, & Package Design : BoardSurfers: Training Insights: Improve Debugging Efficiency Using Procedures In inspectAR-Allegro Flow

    Jasmine
    Jasmine
    Debugging a PCB from a bare schematic and board is a time-consuming task. Using the Augmented Reality (AR) Electronics Platform, inspectAR with the Allegro® PCB Editor flow vastly improves the efficiency of PCB procedural testing by addressi...
    • 12 Jul 2023
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