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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About AMS Partial Design Simulation? It’s in the 16.5 Release!

Partial Design Simulation aims at unifying the PCB and simulation flow by enabling…

• 2 min read
PCB , "capture CIS" , AMS , AMS simulator , Capture CIS , Allegro 16.5 , Allegro 16.2 , partial simulation , PSPICE , design , AMS simulation , Design Entry , SPB16.5 , PCB Capture

Verification

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly…

• 1 min read
Verification IP , ACE , Cortex-A15 , Functional Verification , video , VIP , interconnect monitor , ACE verification , cache coherency , coherency , ARM

Verification

Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up

In a prior Team Verify post, Application Engineer Bin Ju talked about several applications…

• 1 min read
show me , ABV , Functional Verification , Formal Analysis , formal , ADS , Chris Komar , witness trace , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Verification

Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated

Our friend and fellow blogger JL Gray recently published a post with the provocative…

• 2 min read
SystemVerilog , uvm , uvm world , universal verification methodology , UCIS , Accellera , JL Gray

System, PCB, & Package Design 

What's Good About Net Groups in Capture? Check Out the 16.5 Release and See!

A NetGroup is a collection of nets. The nets in a NetGroup can be scalar, vector…

• 2 min read
"capture CIS" , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture Marketplace , electrical constraints , Capture CIS , Capture-CIS , Allegro 16.5 , design , OrCAD , Design Entry , net groups , SPB16.5 , NetGroup , PCB Capture , Schematic

Verification

Everything New is Old … Everything Old is New

The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl…

• 2 min read
gate level , Functional Verification , LEC , RTL , DRC , LVS , EDA , old , gate-level , new , simulation

System, PCB, & Package Design 

What's Good About ADW’s Server? 16.5 Has a Few New Enhancements!

Some of the enhancements to the Allegro Design Workbench (ADW) 16.5 release were…

• 1 min read
PCB , Allegro Design Workbench , Library flow , Allegro 16.5 , design data management , design , "PCB design" , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

Welcome to the next installment in my series about different ways to use the venerable…

• 4 min read
Virtual System Platform , TLM , virtual platform , UART , System Design and Verification , telnet , embedded software , xterm , virtual prototype , software , SystemC , linux , ESL

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 2

In the previous posting Introduction to Classes -- Part 1 we introduced the problem…

• 3 min read
Team SKILL , programming , object orientation , Virtuoso , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!

The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as…

• 2 min read
SCM , Allegro Design Entry , Allegro 16.5 , SPB , BGA , Allegro System Architect (ASA) , design , Design Entry , SPB16.5 , FPGA , FPGA: PCB

System, PCB, & Package Design 

Robert Hanson and Cadence Team Up to Deliver Texas Signal Integrity Event

TeamOrCAD, TeamAllegro and Signal Integrity expert Robert Hanson will continue to…

• 2 min read
PCB , SI , PCB design" , Signal Intregrity , PCB Signal and power integrity , Texas , "PCB SI" , Allegro 16.5 , OrCAD PCB SI , Hanson , Allegro PCB SI , "PCB PI" , Allegro

Analog/Custom Design

Bringing Static Analysis Methods to Mixed Signal Designs

Accurate static analysis and complete coverage of the functional space remain very…

• 2 min read
Static timing analysis , static analysis , mixed signal design , full timing model , STA , timing model , analog , FTM , Mixed-Signal , Signal Integrity , OpenAccess , SPICE , liberty model , .lib

System, PCB, & Package Design 

What's Good About Up-Reving in DEHDL? You Can Easily Do This in 16.5!

All Allegro PCB Editor designers know about the uprev process to migrate PCB .brd…

• 3 min read
PCB , Allegro Design Entry , hierarchy , DEHDL , electrical constraints , uprev , property , Allegro 16.5 , SPB , Design Entry HDL , Front-end PCB design , Design Entry , SPB16.5 , ConceptHDL

Verification

Can Your Verification Survive “Boot Camp”?

In Silicon Valley there is a popular fitness program called "Boot Camp" where people…

• 1 min read
ABV , boot camp , Functional Verification , Formal Analysis , formal , Incisive , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verification

What Does SystemC Mean for Design and Verification?

My colleague Jack Erickson recently published in the Cadence System Design and…

• 3 min read
Virtual System Platform , TLM , uvm world , Functional Verification , Incisive Enterprise Simulator , VSP , C-to-Silicon , SystemC , IES-XL

Verification

Virtual Platform UART Use Number 1: Connecting to an Interactive Terminal

Welcome to the first example of using a UART in a Virtual Platform. For those just…

• 8 min read
Virtual System Platform , virtual platforms , Embecosm , virtual prototypes , UART , System Design and Verification , System Development Suite , xterm , SystemC

Verification

If Only Carl Friedrich Gauss had IntelliGen in 1850

The N-queens issue is a challenging but standard puzzle when it comes to the world…

• 5 min read
N-queens , IntelliGen , Specman , Object Oriented Programming , Functional Verification , Testbench simulation , e , OVM-e , team specman , specman elite , multi-language , Gauss , simulation , Rubik's Cube , AOP , Trailblazer

Verification

UCIS Coverage Standard -- Innovation Means Business

Open solutions are just curiosities until the ecosystem figures out how to turn…

• 1 min read
metric-driven , coverage , Functional Verification , Metric Driven Verification , EDA360 , Incisive , Enterprise Manager , Plan and metrics management , UCIS , Accellera , coverage driven verification (CDV) , MDV

Verification

What I Learned Traveling Across the Silicon Prairie

Inspired by Brian Fuller's cross-country "Drive for Innovation" , last week I jumped…

• 1 min read
Silicon Prarie , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , formal , ADS , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification
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