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AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
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Blog - Post List

Latest blogs

Analog/Custom Design

Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic…

• 2 min read
ADE GXL , ADE XL , mismatch variation , Virtuoso Analog Design Environment , Monte Carlo , mismatch contribution analysis

Whiteboard Wednesdays

Whiteboard Wednesdays - Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays, Jacek Duda provides an informative overview…

• less than a min read
USB performance specs , Whiteboard Wednesdays , IP , USB 3.X , USB controllers , USB 2.0

System, PCB, & Package Design 

Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2…

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of…

• 2 min read
single and multi-fabric design , full wave 3D field solver , Power Integrity , IC package design , 3DEM , Signal Integrity

System, PCB, & Package Design 

Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging…

To maximize yield and achieve optimum quality of your final, manufactured IC package…

• 4 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging and SiP , IC package design , IC Packaging & SiP design , IC packaging documentation , substrate , SiP Layout

Whiteboard Wednesdays

Whiteboard Wednesdays—The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of…

• less than a min read
LPDDR4 , LPDDR , wide i/o , USB , UFS , eMMC , DRAM , AMBA 5 , OCP , Wide I/O2 , CSI-3 , DDR , Soundwire , PCIe and SSIC. , AMBA 4 , eMMC5 , LPDDR3

System, PCB, & Package Design 

What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!

While there are several videos available for Allegro Design Entry HDL (DEHDL) in…

• 1 min read
PCB , Allegro Design Entry , Allegro 16.6 , PCB design videos , electrical constraints , flat schematics , hierarchical schematics , Allegro 16.5 , SPB , Design Entry HDL , Design Entry , ConceptHDL

Analog/Custom Design

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power…

• 2 min read
Analog Design Environment , ADE GXL , ADE XL , Virtuoso , Custom IC Design , Design Migration

System, PCB, & Package Design 

What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!

There are two new use models for PCB designers using Allegro Design Workbench (ADW…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.6 , Allegro Design Workbench , PCB Editor , design data management , design , PCB design , Allegro PCB Editor , ADW

Whiteboard Wednesdays

Whiteboard Wednesdays - Why Cadence Verification IP (VIP) is a Smart Choice for …

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , SoC design , verifying SoCs

Verification

Cadence Announces Verification IP for MIPI SoundWire and C-PHY

Anyone who has been involved in designing mobile devices in recent years is familiar…

• less than a min read
Verification IP , MIPI Alliance , cadence , audio , PureSpec , Slimbus , VIP , MIPI , CSI , M-PCIe , Denali , C-PHY , Soundwire , M-PHY

Whiteboard Wednesdays

Whiteboard Wednesdays - New MIPI Interfaces: Winners or Losers?

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a…

• less than a min read
Whiteboard Wednesdays , M-PCIe , MIPI protocols , USB , mobile interfaces , mobile

Verification

The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures…

• 4 min read
ARM ecosystem , System Design and Verification , electronics design , Internet of Things , ARM , embedded systems

Analog/Custom Design

Fast Yield Analysis and Statistical Corners

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random…

• 3 min read
ADE GXL , ADE XL , fast yield analysis , Virtuoso Analog Design Environment , Monte Carlo , statistical corners

Verification

Randomizing Error Locations in a 2D Array

A design team at a customer of mine started out with Specman for the first time…

• 3 min read
AF , IntelliGen , Specman , e code , stimuli , Generation , Funcional Verification

SoC and IP

RealTek Shows New HiFi-based Codec with Software from Sensory and ForteMedia

Watch these demonstrations of RealTek's new ALC5677 audio codec - which uses HiFi…

• less than a min read
voice recognition , audio , Sensory , microphone , HiFi , Tensilica , ForteMedia , always-on , RealTek

Analog/Custom Design

Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence…

Time just got away from me last month, so here's two months worth of new content…

• 2 min read
AMS , Corners , ADE , ADE-GXL , PVT corners , Custom IC Design , Virtuoso Layout Suite

System, PCB, & Package Design 

Customize Your Menus Dynamically with SKILL in Cadence Allegro 16.6-Based Layout…

Many users of the Allegro, APD, and SiP tools are familiar with the great flexibility…

• 5 min read
IC Packaging and SiP Design , IC packaging SiP Layout , Digital SiP design , IC Packaging & SiP design , IC packaging documentation , IC Package Physical layout and co-design

Whiteboard Wednesdays

Whiteboard Wednesdays—How 2D Solutions Help Close the Memory Wall Gap

In this week's Whiteboard Wednesdays episode, Scott Jacobson deep dives into 2D memory…

• less than a min read
performance , Whiteboard Wednesdays , 2D Memory , DDR4 , UFS , eMMC , power

SoC and IP

MIPI Protocols—Making Mobile Happen at MWC

MIPI protocols are expected to ship in over 4 billion mobile devices this year. That…

• less than a min read
controller IP , Verification IP , Design IP , IP , MIPI Alliance , PHY , BIF , Slimbus , VIP , MIPI , CSI , MWC , semiconductor IP , M-PHY
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