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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About Repeating Myself? With the SPB16.3 Virtual Conference, You'll Know

This is a first for me, basically writing about the same topic. But, the SPB16.3…

• less than a min read
Virtual Conference , SPB 16.3 , Allegroro , PCB design

Verification

Android System Verification - Part 3

In Part 2 of this series on Android System Verification I provided the basics on…

• 4 min read
Specman , android , System Design and Verification

Verification

New FOSS e Language Project: CFS Vision

There is a new free, open source (FOSS) e language project out there called “CFS…

• 7 min read
IEEE 1647 , Specman , Functional Verification , VIP , OVM e , e , CFS Vision , AMIQ , Aspect Oriented Programming , FOSS , eRM , JFreeChart , AOP , IES-XL

Verification

Verification Productivity Is Holding Back Electronic System Level Development Ad…

There is a controversy brewing in our industry, and I'm about to step into it boldly…

• 2 min read
TLM , Functional Verification , System Design and Verification , ESL

Verification

Tech Tip: Setup Your OVM e Environment So Even Your 16 Year Old Can Use Sequence…

A few months ago we introduced the Sequences API in OVM e in the post “ OVM e Sequence…

• 5 min read
IEEE 1647 , Specman , Functional Verification , OVM , OVM e , e , Aspect Oriented Programming , sequences , AOP , IES-XL

Verification

Highlights From ClubT Hertzelia

Over 125 Verification engineers honored us this past Tuesday by attending the annual…

• 2 min read
Specman , Functional Verification , e , ClubT , IES-XL

Verification

Observations From This Autumn's Events

As you may recall I was involved in producing several events this past fall . Allow…

• 2 min read
AMS , Specman , CDNLive , Functional Verification , Twitter , ClubT , ESL , IES-XL , Trailblazer

SoC and IP

Guide to Denali's Synthesizable DDR PHY

Click on a frame for slideshow view. Enjoy! …

• less than a min read

System, PCB, & Package Design 

What's Good About the SPB16.3 Release? Join The Virtual Conference 12/02/09 and See

You will NOT want to miss this event! The first ever Virtual Trade Show for the SPB…

• 4 min read
PCB , IC Packaging and SiP Design , Virtual Conference , SPB 16.3 , Allegroro , OrCAD , PCB design

Analog/Custom Design

Things You Didn't Know About The Rhinovirus and ViVA (Part 3)

Okay, so I really have no idea how to tie those 2 things together, but I ran across…

• 3 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

Interview With Teradyne on Metric Driven Verification

Welcome to the first TeamMDV blog. We are excited to bring you information, tips…

• 3 min read
Functional Verification , Incisive , SoC , Enterprise Manager , Enterprise Planner , MDV , IES

Verification

Android System Verification Part 2

In Part 1 of this series on Android System Verification I provided the basics about…

• 3 min read
android , System Design and Verification , Java , ISX , Monkey

Verification

We and Our Competitors Agree (Well, Almost!)

It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes…

• 2 min read
DAC , ICE , System Design and Verification , Palladium , SoC , FPGA

System, PCB, & Package Design 

What's Good About Cadence Online Support? – Here’s My List!

My good friend and fellow blogger - Bob Dwyer - recently posted on the new Cadence…

• 2 min read
Support , PCB design , Online Support

Verification

IntelliGen Lab Now Live on Xuropa - See What You Are Missing!

Team Specman guesstimates that a majority of users have migrated to "IntelliGen"…

• 2 min read
IntelliGen , Specman , Functional Verification , Cadence VIP portfolio , e , DVcon , Xuropa , IES-XL

Verification

Android System Verification Part 1

From time to time I hear or read stories about how engineers find ways to apply Specman…

• 5 min read
Specman , android , System Design and Verification , Virtual Platforms , verification

Verification

Ten Things I've Learned About Formal

2009 is the tenth year that I've spent at least a portion of my time responsible…

• 2 min read
verifier , Enterprise , Functional Verification , formal , Incisive , IEV

Verification

"ClubT" Herzelia Israel Verification Seminar Invitation 17 November

Specmaniacs Based In Israel, Please join us for a day of in-depth presentations and…

• less than a min read
IntelliGen , Specman , verification strategy , Verification methodology , OVM ML , Functional Verification , simvision , VIP , OVM e , e , Enterprise Manager , Enterprise Planner , ClubT , IES-XL

Digital Design

Find, Fix And Learn With Cadence Online Support

We recently rolled out a new online support mechanism that replaces Sourcelink called…

• 1 min read
Sourcelink , Cadence Online Support , Digital Implementation
CDNS - Fix Layout Hompage