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Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan 8 Jan 2026 • less than a min read

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate 6 Jan 2026 • 1 min read

news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan 22 Dec 2025 • less than a min read

news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar 17 Dec 2025 • 4 min read

IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

cdns - all_blogs_categories

All 6201
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Artificial Intelligence 24
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Digital Design 441
Learning and Support 58
RF Engineering 115
SoC and IP 419
System, PCB, & Package Design 999
Verification 1300
Cadence Japan 10

CFD（数値流体力学) 45
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カスタムIC／ミックスシグナル 193
PCB、IC封装：设计与仿真分析 136
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RF /マイクロ波設計 45
Spotlight Taiwan 61
The India Circuit 92
定制IC芯片设计 79
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Whiteboard Wednesdays 253

Blog - Post List

Latest blogs

Verification

New Technical Blog on e & Specman Technology

Specmaniacs of the world: rejoice! Members of Team Specman have just launched their…

jvh3 10 Dec 2008 • less than a min read

IEEE 1647 , Specman , e

Verification

Constraint layering - Fine Tuning Your Environment - Part 1

In today's environment of ever growing complexity and ever shrinking schedules,…

teamspecman 10 Dec 2008 • 3 min read

IEEE 1647 , SystemVerilog , Specman , verification strategy , Verification methodology , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Verification

New e / Specman Workshops Available Now

In response to the continual growth in the e /Specman user community, Team Specman…

teamspecman 10 Dec 2008 • 2 min read

workshops , IEEE 1647 , Specman , metric driven verification (MDV) , Functional Verification , Testbench simulation , MDV techtorial , OVM e , Coverage-Driven Verification , e , Kit , coverage driven verification (CDV) , eRM , IES

Verification

New Blog - All About e & Specman

End-users of e , Specman, Incisive Enterprise Simulator (IES), e RM/OVM e , and…

teamspecman 10 Dec 2008 • 1 min read

IEEE 1647 , Specman , verification strategy , metric driven verification (MDV) , Functional Verification , Testbench simulation , OVM e , Coverage-Driven Verification , e , coverage driven verification (CDV) , eRM , Incisive Enterprise Simulator (IES) , IES

System, PCB, & Package Design

What's Good About SPB16.2 OrCAD Capture? Many Usability Enhancements!

There are enormous usability updates in the SPB16.2 release of OrCAD Capture. From…

Jerry GenPart 10 Dec 2008 • 7 min read

SPB 16.2 , OrCAD , PCB design

Analog/Custom Design

What's New With Virtuoso?

If you were wondering what's new with Virtuoso you may want to check out the latest…

deana 8 Dec 2008 • less than a min read

MMSIM , Floorplanning , Virtuoso IC 6.1.3 , Virtuoso , RF design , Custom IC Design

Verification

Metric Driven System Level Verification

I have the great honor of introducing a wonderful paper on system level verification…

jasona 5 Dec 2008 • 1 min read

System Design and Verification , ARC International , ISX

Verification

VMM Users -- Welcome to the OVM!

VMM users -- welcome to the OVM! We've been talking together about the benefits…

Adam Sherer 4 Dec 2008 • 3 min read

SystemVerilog , Verification methodology , Functional Verification , OVM , VIP , e , eRM , OVMWorld

Digital Design

3 Reasons Why You Will Want to Download Encounter 8.1

Today is a big day in Digital Implementation land here at Cadence. Looking around…

BobD 3 Dec 2008 • less than a min read

Flows , SoC-Encounter 8.1 , Low-Power , Digital Implementation , Floorplanning and Prototyping

System, PCB, & Package Design

What's Good About the SPB16.2 Cross Referencer? Active Links in the Schematic!

That's right - an often requested feature from several customers has now been implemented…

Jerry GenPart 3 Dec 2008 • 2 min read

SPB 16.2 , PCB design

Digital Design

Innovate Your Way Out of Recession With the New Encounter!

It's official! The U.S. economy has been in a recession for the past year. …

RahulD 3 Dec 2008 • 2 min read

Static timing analysis , Early Rail Analysis , SoC-Encounter , Digital Implementation forums , First Encounter , SoC-Encounter 8.1 , Signoff Analysis , STA , encounter , Cadence Encounter Power System , Digital Implementation , CeltIC NDC , Global Timing Debug , Encounter Timing System , SSTA , Floorplanning and Prototyping , "SoC-Encounter"

Verification

News From the IP '08 Conference

My colleagues on the Verification IP team have been honored to present at the annual…

jvh3 3 Dec 2008 • 3 min read

HW/SW , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , VIP , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , Verification IP modeling , ISX