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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Verification

Can Your Verification Survive “Boot Camp”?

In Silicon Valley there is a popular fitness program called "Boot Camp" where people…

• 1 min read
ABV , boot camp , Functional Verification , Formal Analysis , formal , Incisive , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verification

What Does SystemC Mean for Design and Verification?

My colleague Jack Erickson recently published in the Cadence System Design and…

• 3 min read
Virtual System Platform , TLM , uvm world , Functional Verification , Incisive Enterprise Simulator , VSP , C-to-Silicon , SystemC , IES-XL

Verification

Virtual Platform UART Use Number 1: Connecting to an Interactive Terminal

Welcome to the first example of using a UART in a Virtual Platform. For those just…

• 8 min read
Virtual System Platform , virtual platforms , Embecosm , virtual prototypes , UART , System Design and Verification , System Development Suite , xterm , SystemC

Verification

If Only Carl Friedrich Gauss had IntelliGen in 1850

The N-queens issue is a challenging but standard puzzle when it comes to the world…

• 5 min read
N-queens , IntelliGen , Specman , Object Oriented Programming , Functional Verification , Testbench simulation , e , OVM-e , team specman , specman elite , multi-language , Gauss , simulation , Rubik's Cube , AOP , Trailblazer

Verification

UCIS Coverage Standard -- Innovation Means Business

Open solutions are just curiosities until the ecosystem figures out how to turn…

• 1 min read
metric-driven , coverage , Functional Verification , Metric Driven Verification , EDA360 , Incisive , Enterprise Manager , Plan and metrics management , UCIS , Accellera , coverage driven verification (CDV) , MDV

Verification

What I Learned Traveling Across the Silicon Prairie

Inspired by Brian Fuller's cross-country "Drive for Innovation" , last week I jumped…

• 1 min read
Silicon Prarie , Joe Hupcey III , ABV , Functional Verification , Formal Analysis , formal , ADS , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verification

Verifying AMBA® 4 ACE Designs – Cadence is Ready to Help, Now

ACE is here. Are you ready? Designers of multimedia smartphones, tablets, and other…

• 1 min read
Verification IP , ACE , Functional Verification , VIP , tablet , AMBA , Smartphone , EE Times

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 1

In the previous couple of SKILL for the Skilled postings, we looked at some of the…

• 3 min read
Sodoku , Team SKILL , programming , classes , object orientation , Virtuoso , object system , Lisp , Custom IC Design , SKILL++ , SKILL , Allegro

Verification

IP Cannot be an Efficient Abstraction Level Without SystemC!

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction…

• 3 min read
High-Level Synthesis , IP , TLM , RTL , abstraction , IP re-use , EDN , SoC , IP assembly , system design , SystemC , HLS , System Design and Verification

RF Engineering

Measuring Fmax for MOS Transistors

The following question has come up in comments: "How do I measure F max for an MOS…

• 3 min read
RF , RF Simulation , analog/RF , Circuit simulation , RFIC , bipolar transistor , MOS transistors , measuring Fmax , Virtuoso , Fmax , RF design , fmax testbench , simulation , bsim3v3

Digital Design

Five-Minute Tutorial: The Encounter Digital Implementation Cell Viewer

How many times have you wanted to look at a certain standard cell in the Encounter…

• 1 min read
EDI , Layout Control , encounter , EDI 10.1 , Digital Implementation , five minute tutorial , Cell Viewer

Verification

Virtual Flash Memory Gets Real

This week's Flash Memory summit will not only highlight the IP Cadence delivers,…

• 1 min read
Virtual System Platform , IP , Memory , virtual platforms , TLM , virtual prototypes , TLM 2.0 , flash memory , Incisive Software Extensions , ISX , Flash Memory Summit , System Design and Verification

System, PCB, & Package Design 

What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

Currently, many of the SPB products support extended nets, better known as Xnets…

• 8 min read
PCB SI , PCB , PCB Layout and routing , IC Packaging and SiP Design , SI , ECSets , Allegro Design Entry , Constraint-driven PCB Design flow , diff pairs , Design Rule Checker , Routing , Signal Intregrity , DEHDL , Analog and RF SiP design , Digital SiP design , electrical constraints , SigXP UI , PCB Signal and power integrity , High Speed , APD , PCB power integrity , Allegro Design Workbench , Allegro 16.5 , PCB Editor , Design Entry HDL , advanced package designer , ASA , Layout , Allegro System Architect (ASA) , Xnets , Front-end PCB design , design , PCB Signal integrity , Allegro PCB SI , PCB design , Design Entry , SPB16.5 , Allegro PCB Editor , differential pairs , SI analysis and modeling , Differential Pair Support , ConceptHDL , Schematic , Allegro

RF Engineering

Guidelines for Setting Pnoise/HBnoise Sidebands to Get Accurate Results

I get quite a few questions from designers along the lines of "How do I set the number…

• 2 min read
RF , RF Simulation , analog/RF , HBnoise , shooting newton , HB , Spectre RF , pnoise , RF spectre spectreRF , spectreRF , RF design , harmonic balance , pss

Verification

A Must Read: the ARM Cortex-A Programmer's Guide

For the last couple of years, I have been getting a lot of e-mail from different…

• 2 min read
ARM Cortex-A , virtual platforms , programmer's guide , virtual prototypes , Cortex-A , virual platform , ARM Architecture , ARM , linux , System Design and Verification

SoC and IP

Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI…

• 1 min read
controller IP , Design IP , IP , PCI Express 3.0 , Gen3 , video , PCIe , PCIe Gen3 , SR-IOV , PCI Express

System, PCB, & Package Design 

What's Good About PCB SI Design Setup and Audit? 16.5 Has MANY New Enhancements!

Many of the problems that customers encounter today when running a signal integrity…

• 10 min read
PCB SI , IC Packaging and SiP Design , SI , SiP , Signal Intregrity , SigXP UI , PCB Signal and power integrity , "PCB SI" , Allegro 16.5 , PCB Editor , "PCB design" , Allegro PCB SI , PCB design , SPB16.5 , SI analysis and modeling

Verification

The Return of the Son of Real-World Assertions

I've received some nice feedback on my previous two posts about real-world situations…

• 3 min read
ABV , Functional Verification , formal , assertions , Assertion-based verification

Analog/Custom Design

Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in…

In my previous blogs , I talked about productivity enhancing features of Virtuoso…

• 2 min read
analog , ADE , Virtuoso , Analog Design Environment , Virtuoso datasheets , Schematic Editor , Custom IC Design , datasheets
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