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SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

IEDM: TSMC on 3nm Device Options

At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and…

• 4 min read
TSMC , IEDM

System, PCB, & Package Design 

BoardSurfers: Leveraging IPC-2581 Spec Element Capabilities to Streamline Design…

If you are a PCB designer and follow IPC-2581 guidelines to design a board, this…

• 3 min read
Manuafacturing , PCB Editor , 17.4-2019 , IPC-2581

Breakfast Bytes

DesignCon 2020: SI, PCB, Packaging, Photonics

Next Tuesday through Thursday, January 28 to 30, DesignCon 2020 takes place in the…

• 3 min read
PCB , DesignCon , Signal Integrity , OrCAD , Sigrity , Allegro

System, PCB, & Package Design 

DATA Pulse: Simplify Your ECAD Data Release Process While Ensuring Process Contr…

Do you dread your ECAD to PLM publishing process? If yes, worry not. We have a solution…

• 1 min read
System Capture , allegro edm , PCB design , Pulse , PLM

Breakfast Bytes

IEDM: Automating DTCO for 3nm

At IEDM in December, Lars Liebmann of TEL presented Design Technology Co-Optimization…

• 4 min read
3nm , IEDM , DTCO

定制IC芯片设计

Virtuosity：Modgen中的布局重用流程

Modgen 现在支持布局重用流. 请继续阅读，了解如何使用此功能通过减少创建 Modgen 的时间和精力来提高版图效率.

• less than a min read
Chinese blog , Modgen On Canvas , ICADVM18.1 , MODGEN , Layout Suite , Layout , Virtuoso , Virtuosity , Layout design , Custom IC Design , modgens , Virtuoso Layout Suite , Custom IC

System, PCB, & Package Design 

IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

When you need to make an edit to a component, whether that is the BGA footprint in…

• 8 min read
Allegro Package Designer

Breakfast Bytes

A Big Problem with Big Data

I happened to read a blog post that referred to a 2018 paper in The Annals of Applied…

• 5 min read
deep learning , big data

定制IC芯片设计

技术性：器件的自动布局和布线 — 基于行的器件放置

Device-level automatic placer允许您以约束和网格兼容的方式放置器件和设备组. 您可以使用交互式设备放置选项半自动放置设备.

• less than a min read
Chinese blog , Automatic Placement , Virtuoso Placer , Auto P&R , Virtuosity , Virtuoso Placement , Custom IC Design

Breakfast Bytes

Sunday Brunch Video for 19th January 2020

https://youtu.be/O90mUZyWIeE Made at Lick Observatory (camera Carey Guo) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

Off-Topic: Picas, Points, and Printing

Monday is Martin Luther King, Jr Day, and Cadence will be off. Breakfast Bytes will…

• 7 min read
offtopic , printing

定制IC芯片设计

Virtuoso视频日记：简单的方法来解决 复杂的问题——schTraceNet

基于SKILL函数 schTraceNet 定义一个回调函数，将被探测的信号带入到下一层，这样就可以解决层次化原理图设计中遇到的复杂问题。

• less than a min read
schTraceNet , Chinese blog , Virtuoso Schematic Editor , ICADVM18.1 , Net Tracing , video , tracing a net , Virtuoso , Schematic Editor , Virtuoso Video Diary , Probing , Circuit Design , Probes assistant , Custom IC Design , Custom IC , IC6.1.8 , Schematic , net area

Breakfast Bytes

Emerging Memory

SNIA, the Storage Networking Industry Association, organized a webinar recently with…

• 5 min read
Memory , optane , MRAM , persistent memory , 3dxpoint

The India Circuit

Of Brains and Computers: Keynote by Dr Jan Rabaey

One of the industry’s biggest events, the VLSI Design Conference, took place in Bangalore…

• 3 min read
janrabaey , VLSID2020 , BWRC

Breakfast Bytes

5G in 2020

There is a famous quote, attributed to Mark Twain but more likely said by his friend…

• 6 min read
5G , CES , ces2020

System, PCB, & Package Design 

BoardSurfers: DFF - Three Steps to Perfect Mask Defined Padstacks in Your PCB

We will of course not venture into the finer points of the debate about mask-defined…

• 3 min read
PCB Editor

System, PCB, & Package Design 

IC Packagers: The Default Bond Wire Profile - PROFILE1 (And Three Reasons Why Not…

For those of you who do wire-bond package substrate – whether you’re designing a…

• 6 min read
Allegro Package Designer

Breakfast Bytes

Mark Cuban on Media and AI

At CES there was a session in which Mark Cuban was interviewed. As he pointed out…

• 4 min read
CES , ces2020 , AI

定制IC芯片设计

Virtuosity: 针对高阶工艺节点的器件级布线工具— 树型布线流程

本博客是Virtuoso器件级布线系列博客的最终篇，将介绍树干和树枝形成树的完整过程，通过这种类比方式，便于用户全面了解Tree Route 的流程及其功能. …

• 1 min read
Chinese blog , tree routing , structured routing , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , Mixed-Signal , Tree Route , Layout Suite , trunk creation , Generate Trunk , Custom IC Design , Virtuoso Layout Suite , Custom IC
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