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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

PCB解析／ICパッケージ解析

Sigrity and Systems Analysis 2024.0 (2024年5月リリース) 新機能ハイライト

Sigrity & Systems Analysis (SIGRITY/SYSANLS) 2024.0リリースが Cadence Downloads サイトからダウンロード可能となりました…

• 3 min read

Cloud

Cloud Tech Day: Pioneering the Future of Managed Cloud Solutions for Chip Design

The recently held Cadence Cloud Tech Day event was a testament to the power of collaboration…

• 3 min read
featured , Managed Cloud , OnCloud Marketplace , True Hybrid Cloud , cadence cloud , z3 , palladium and protium cloud

Corporate News

Green Bytes and Sustainable Bites: Dietary Choices for Environmentally Friendly Electronics…

Understanding ESG and Its Connection to Food Environmental, social, and governance…

• 3 min read
featured , esg , sustainability

カスタムIC／ミックスシグナル

Virtuoso Studio IC23.1: Net Tracerで設計レビューを効率化

By Sandhya P S, Sr Education Application Engineer Translator: Masaru Yasukawa このブログでは…

• 1 min read
IC 23.1 , Analog Design Environment , Cadence blogs , Virtuoso Studio , custom/analog , cadence , review , design review , analog , Virtuoso RF , Layout EXL , training , Layout Suite , Virtuoso Analog Design Environment , training bytes , Layout , Virtuoso , design , Virtuoso Video Diary , Analog Layout Automation , Analog Layout , japanese blog , Custom IC Design , Net Tracer , Virtuoso Layout Suite , Custom IC , blog

Analog/Custom Design

Virtuoso Studio IC23.1 ISR9 Now Available

Virtuoso Studio IC23.1 ISR9 production release is now available for download.

• 1 min read
Cadence blogs , IC Release Blog Announcement , Virtuos Studio , Cadence Community

System, PCB, & Package Design 

The Mechanical Side of Multiphysics System Simulation

Introduction Multiphysics is an integral part of the concepts around digital twins…

• 3 min read
EM Analysis , data center , system simulation , Thermal Analysis , multiphysics

Life at Cadence

One Cadence: From Idaho to Silicon Valley with Pride

Recently, I traveled from my hometown and remote work location in southeast Idaho…

• 4 min read
Culture , featured , Cadence Culture , Pride , ERG , LGTBQ+ , DEIatCadence

Computational Fluid Dynamics

Natural Gas Boiler Optimization to Improve Efficiency and Reduce Emissions

Improved boiler designs are critical in the quest to produce energy more efficiently…

• 5 min read
Multi-objective Optimization , cadencelive silicon valley , Natural Gas Boiler , Cadence CFD , Fidelity Pointwise , SU2

System, PCB, & Package Design 

OrCAD X – The Anytime Anywhere PCB Design Platform

OrCAD X is the next-generation integrated PCB design platform. It brings to you a…

• 1 min read
PCB , OrCAD X Capture , innovation , PSpiceA/D , PSPICE , Layout , PCB design , OrCAD X Presto , OrCAD X , Constraints , simulation , Schematic

SoC and IP

DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers

The demand for higher-performance computing is greater than ever. Cutting-edge applications…

• 2 min read
ddr5 , Design IP , IP , gddr6 , PHY , 3nm , MRDIMM , GDDR , memory IP , Denali , Design IP and Verification IP , DDR

Computational Fluid Dynamics

Theoretical Foundations of k-ω Menter-Shear Stress Transport Turbulence Model

Key Takeaways Widely recognized in turbulence modeling, the k-ω (M-SST) model uses…

• 6 min read
CFD , turbulence , Computational Fluid Dynamics , Fidelity CFD , CFD Applications

Data Center

Cadence Accelerates the Sustainability of AI Factories with NVIDIA Omniverse

AI is transforming industries at an unprecedented pace, and the demand for efficient…

• 4 min read
featured , NVIDIA , data center , Reality , digital twin

Digital Design

Is Design Power Estimation Lowering Your Power? Delegate and Relax!

The traditional methods of power analysis lag by various shortcomings and challenges…

• 3 min read
digital badge , estimation , annotation , Joules , Analysis , training bytes , RTL Solution , power , online training , Online Support , Joules RTL Design Studio

Data Center

Don't Sacrifice Your Data Center's Sustainability

Balancing Availability, Capacity, and Energy Efficiency in Modern Data Centers In…

• 4 min read
CFD , futurefacilities , data center , digital twin , simulation software , cooling , Liquid Cooling , Cadence Reality DC

Corporate News

Shaping the Future of Automotive Safety with V2X and Cadence Solutions

In recent years, the automotive industry has witnessed a technological evolution…

• 3 min read
Automotive , featured , chiplet , v2x

Computational Fluid Dynamics

Embracing the Future of CFD with Cadence's Millennium M1 Supercomputer

In a recent episode of the Aerospace and Defense Technology Podcast , host Woodrow…

• 1 min read
CFD , frank ham , Millennium M1 , podcast

Verification

Replay Attack Over IP Networks and its Protection Mechanism

In today's interconnected world, ensuring the security of data transmitted over networks…

• 3 min read
security , Verification IP , Internet protocol , VIP , IPSec , Design IP and Verification IP , verification

Digital Design

Technical Webinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

In this training webinar, we explore the concepts of RTL design, design verification…

• 2 min read
COS , IMC , IC , DFT , Integrated Metrics Center , IP , chip design , webinars , verification engineers , Xcelium Logic Simulator , training , Mixed-Signal , Logic Design , coverage analysis , RTL-to-GDSII FrontEnd , training bytes , system verilog , Freshly Graduate , Cadence RTL-to-GDSII Flow , Technical webinar , RTL2GDSII , RTL design , online training , HLS , VHDL , vManager , Verisuim

System, PCB, & Package Design 

BoardSurfers: Some Wisdom from Designing for a High-Volume Production OEM

At what stage in the design cycle do you start to think about the PCB material costs…

• 9 min read
Allegro X PCB Editor , BoardSurfers , Allegro X Advanced Package Designer , SPB , PCB Editor , PCB design , allegro x , Allegro
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