Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

定制IC芯片设计

Virtuosity：回顾2019年Virtuoso ADE Product Suite 及 Virtuoso Visualization and Analys…

对于 Virtuoso®ADE Product Suite 和 Virtuoso® Visualization and Analysis 而言，2019 年是非常重要的一年…

• 2 min read
Chinese blog , Cadence blogs , ICADVM18.1 , ADE Explorer , virtuoso visualization and analysis , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler

Breakfast Bytes

Sunday Brunch Video for 12th April 2020

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: From Castles…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 基础二：DFx规则设定

当布线过程中或者布线结束时，发现器件布局不合理，我们将进行繁琐的调整工作。对于复杂PCB，这个调整可能会占用我们整个上午的时间，甚至更久。 如果设计者在布局开始时…

• less than a min read
PCB , Chinese blog , training , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro , 专家培训

Digital Design

Joules – Power Exploration Capabilities

Several tools can generate power reports based on libraries & stimulus. The issue…

• 1 min read
Low Power , Joules , Logic Design , Power Analysis

Digital Design

Exploring Genus-Joules Integration is just a click away!!

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize…

• less than a min read
Low Power , Genus , Joules , Logic Design , Power Analysis

Breakfast Bytes

Designing Chips for Hyperscale Data Centers: Tools

Yesterday's post, Designing Chips for Hyperscale Data Centers: IP , covered the high…

• 5 min read
cloud , cadence cloud , datacenter

Digital Design

Genus Synthesis Solution – Introduction to Stylus Common UI

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus…

• 1 min read
Genus , Logic Design , common , stylus

Breakfast Bytes

Designing Chips for Hyperscale Data Centers: IP

Last week I wrote two posts about the progression from the first commercial computers…

• 5 min read
Design IP , IP , datcenter , Ethernet , 112g , SerDes

Digital Design

Quantus' Substrate Noise Analysis Functionality: RF Spurs Impacting Your Performance…

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence…

• 3 min read
5G , RF , Smart View , SNA , extracted view , Virtuoso , Spectre , qrc , Liberate , signoff , Quantus

Breakfast Bytes

Online Support? There's an App for That!

You are probably working from home. So is pretty much everyone at Cadence, too. This…

• 3 min read
support portal , support app , Support , Cadence support

Learning and Support

Learn SVA If You Know PSL and Learn PSL If You Know SVA

Training Bytes, Cadence’s self-paced learning videos, are the solution for you to…

• 1 min read
video , Support , psa , training bytes , SVL , sva learning channel

Academic Network

Remotely Using Cadence Tools and Licenses (part 2)

After we have shown how to get remote access to Cadence licenses and tools , the…

• 4 min read
Cadence Academic Network , Cadence Online Support , Cadence Online Courses , iLS , Rapid Adoption Kits , LinkedIn

System, PCB, & Package Design 

BoardSurfers: Training Insights: Loading SKILL Programs Automatically

Imagine you are on a vacation with your family, and suddenly, your phone starts buzzing…

• 2 min read
Cadence SKILL , Allegro PCB Editor , Allegro Skill

System, PCB, & Package Design 

IC Packagers: A New Option in Bond Finger Solder Mask Openings

If you design wire bond packages, you’re familiar with the need for the bond fingers…

• 4 min read
Allegro Package Designer

Breakfast Bytes

The Dynamic Duo

In the DC Comics world, the "Dynamic Duo" are Batman and Robin. In the Cadence product…

• 5 min read
dynamic duo , protium x , palladium z1 , Protium , Palladium , Emulation , FPGA prototyping

Digital Design

Innovus Implementation System: What Is Stylus UI?

Hi Everyone, Many of you would have heard about the Cadence Stylus Common UI and…

• less than a min read

Analog/Custom Design

Virtuoso Meets Maxwell: What About My Die That Has No Bumps, Only Pad Shapes? How…

If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad…

• 6 min read
ICADVM18.1 , die export , VRF , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Package Design in Virtuoso , die , System Design Environment , shape-based die , RF design , shape , Custom IC , VMM

Breakfast Bytes

From Castles and Moats to Zero-Trust Networking

The way that we handle enterprise security has changed dramatically. In the days…

• 5 min read
security , zero trust networking , single sign-on

定制IC芯片设计

Virtuoso视频日记：“Training bytes”助推知识传播—第1部分

本文将以简短的方式介绍 Cadence Education Services网站，让您了解其已上线的一些在线培训课程以及Virtuoso产品特定功能相关的文章。

• 1 min read
Chinese blog , training bytes , Virtuoso , Virtuoso Video Diary , Virtuoso Layout
CDNS - Fix Layout Hompage