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Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
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Blog - Post List

Latest blogs

Breakfast Bytes

What’s for Breakfast? Preview September 12th to 16th (video)

https://youtu.be/eDeD0mg7D54 Monday: My review of Electronic Design Automation…

• less than a min read
CDNLive , palladium z1 , AMD , H.265 , IEEE 802.3 , cdnlive boston , Ethernet , Emulation , codec , netflix , h.264 , vp9 , video codec , darpa

Breakfast Bytes

Cadence's History with MIPI

I talked last week to Kevin Yee, Sachin Dhingra, and Moshik Rubin about the history…

• 6 min read
Automotive , MIPI , mipi devcon , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Cadence Hierarchical CNN Design

In this week's Whiteboard Wednesdays video, Michelle Mao talks about Cadence hierarchical…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , CNN

Breakfast Bytes

SiFive: a RISC-V Fabless Semiconductor Company

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. Jack is…

• 3 min read
risc-v , fabless , sutter hill ventures , freedom unleashed , freedom everywhere , sifive , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Concurrent Team Design Capability (Reason 2…

Use teamwork to get off the critical path! When (not if) change happens or scope…

• 3 min read
Allegro 17.2 , Symphony , Real Time Design , PCB design , Why Move Up to 17.2

System, PCB, & Package Design 

Cadence Online Support — Empowering Learning! New Features from July 2016

Lots of documents are posted on Cadence Online Support on regular basis. Let us take…

• 2 min read
cadence online , "PCB design" , application note , Allegro

Breakfast Bytes

CDNLive Boston Overview

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were…

• 6 min read
CDNLive , Power Integrity , cdnlive boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

RISC-V Gathering Momentum

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think…

• 4 min read
krste asonovic , risc-v , codasip , NVIDIA , google , andes , cortus , Breakfast Bytes , sifive , hp enterprise

Breakfast Bytes

Happy Birthday, HP 12c—35 Years and Counting

Last year was the 50th anniversary of Moore's Law. One consequence of Moore's Law…

• 3 min read
hewlett-packard , hp 12c , CMOS , hp12c , calculator , Breakfast Bytes

Verification

DisplayPort 8K in Olympics 2020

If you’re anything like me, you’ve spent the last couple of weeks glued to the TV…

• 3 min read
Verification IP , VIP , DisplayPort , Design and Verification IP , Olympics

Breakfast Bytes

What’s for Breakfast? Preview September 6th to 9th (video)

https://youtu.be/lD8VFUNds7o Monday: Labor Day. Tuesday: CDNLive Boston. I…

• less than a min read
risc-v , acquila , CDNLive , MIPI , Power Integrity , open cellular , cdnlive boston , mipi devcon , Facebook , Signal Integrity , sifive

Breakfast Bytes

MIPI SoundWire

The MIPI Alliance exists to standardize widely used interfaces in mobile, such as…

• 3 min read
USB Type-C , MIPI SoundWire , MIPI , lightning , Soundwire , RealTek

Analog/Custom Design

Virtuoso Video Diary: Introducing WSP Manager

Are you an advanced node layout or CAD engineer trying to find a methodology for…

• 2 min read
Routing , WSP , Rapid Adoption Kit , Advanced Node , Virtuoso Video Diary , Custom IC Design , Virtuoso Layout Suite

Whiteboard Wednesdays

Whiteboard Wednesdays - Application-Optimized DDR PHYs

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty takes a closer look…

• less than a min read
Whiteboard Wednesdays , memory subsystems , memory IP , DDR IP , DDR PHY

System, PCB, & Package Design 

Sneak Peek: Discussion Topics for Signal and Power Integrity Expert Panel at CDNLive…

Who? Istvan Novak - senior principal engineer at Oracle Kevin Roselle -…

• 2 min read
Power Integrity , cdnlive boston , Signal Integrity , PCB design

Breakfast Bytes

Aging and Self-Heating in FinFETs

At CDNLive in India, Cadence's Hany Elhak discussed aging and self-heating, and how…

• 3 min read
failure , CDNLive India , Spectre , self-heating , aging , FinFET

SoC and IP

HoloLens Is at the Tip of the Tensilica Iceberg, With Processors That Scale to Any…

Microsoft provided details of their HoloLens HPU at HotChips this week, revealing…

• less than a min read
IP , controller , Tensilica , augmented reality

Breakfast Bytes

Piloted Driving: Audi's View

I hope it isn't a surprise to anyone reading this blog that the share of a vehicle…

• 3 min read
Automotive , Audi , automotive electronics , imec , itf brussels , itf

Breakfast Bytes

A Raven Has Landed: RISC-V and Chisel

In Game of Thrones, ravens are George RR Martin's way of getting information around…

• 4 min read
risc-v , riscv , chisel , raven , UC Berkeley , Breakfast Bytes
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