Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

• 2 min read
PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Analog/Custom Design

Things You Didn't Know About Virtuoso: Help Us to Help You

There is a team at Cadence working on developing the next generation of Cadence documentation…

• less than a min read
Virtuoso , Cadence Help , online documentation , Cadence support

System, PCB, & Package Design 

Manage All Design Variant Options for Your Package Substrate Seamlessly Using 16…

Stacked memory is becoming increasingly common in IC package substrates; with that…

• 2 min read
IC Packaging and SiP Design , stacked dies , SiP , IC Package , IC Packaging , SiP Design , design variants , package design , SiP Layout

SoC and IP

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

• 2 min read
DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on

Whiteboard Wednesdays

Benefits of Designing Your SoC with a Multi-Protocol PHY

In this week's Whiteboard Wednesday video, William Chen explains the many benefits…

• less than a min read
Whiteboard Wednesdays , IP , PHY , SoC , multi-protocol

SoC and IP

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Analog/Custom Design

Virtuosity: 14 Things I Learned in May 2015 by Browsing Cadence Online Support

Cadence Documentation 1. Cadence Documentation Survey Cadence is committed…

• 4 min read
ADE XL , Virtuoso , Spectre

Verification

Designing a Google Ara Module and Worrying About MIPI UniPro?

So you've looked at Google project ARA and you have the most brilliant idea for a…

• 1 min read
Verification IP , UniPro , Ara , VIP , MIPI , google , TripleCheck

Verification

Aargh!!! How Can I Read Arguments from the Command Line Without argv?

Many times a user would like to be able to modify the behavior of a program based…

• 3 min read
Specman , Functional Verification , e language , simulation

Verification

Multi-Language Verification Environment (#4)—Multi-Language Hierarchy

In the previous posts in this series on Multi-Language Verification Environment,…

• 2 min read
uvm , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Digital Design

Five-Minute Tutorial: The Innovus Standard Flow

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface…

• less than a min read
design flow , Digital Implementation , Innovus , five minute tutorial

Verification

Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi…

In the previous blog post , we demonstrated connecting a checker implemented in SystemVerilog…

• 3 min read
SystemVerilog , uvm , multi-language verification , UVM Scoreboard , verification

Verification

DAC 2015 – Join Us to Experience the Continuum of Verification and System Development…

The biggest yearly event in electronic design automation (EDA) is due to take over…

• 8 min read
cadence , EDA , Moscone Center , DAC 2015 , verification , system development

Verification

It’s Time to Modernize Debug Data and It’s Happening at DAC

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog…

• 2 min read
Verdi , debug , simvision , VCs , Indago , Debussy , Questa , Incisive Enterprise Simulator (IES) , IES

Whiteboard Wednesdays

Whiteboard Wednesdays—What's a Configurable Processor?

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basics of Tensilica…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , configurable processor

Digital Design

Five-Minute Tutorial: Innovus User Interface Tips

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System…

• less than a min read
UI , Digital Implementation , Innovus , five minute tutorial

Verification

How Ethernet Standards Are Born

I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to…

• 5 min read
Verification IP , 802.3bp , Ethernet standards , Automotive Ethernet , Ethernet , 802.3 , Marris

Verification

Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using…

In the previous blog post , we created a simple multi-language verification environment…

• 3 min read
IEEE 1647 , uvm , methodology , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Verification

Multi-Language Verification Environment—Getting First Run in Few Minutes

Seems that by now, every one in the industry realizes that multi-language verification…

• 2 min read
uvm , methodology , e , e language , UVC , multi-language
CDNS - Fix Layout Hompage