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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays—Ethernet in Cars

In this week's Whiteboard Wednesdays, Arthur Marris introduces the next big thing…

• less than a min read
communication protocol , Automotive Ethernet , Ethernet , open standard , interoperability

Verification

Troubleshooting Incisive Errors/Warnings with nchelp/ncbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
nchelp , Incisive , error , xcelium simulator , troubleshooting , mnemonic , xcelium , utilities , xmhelp

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Move Lines/Text to Different Classes? Check…

Beginning with the 16.6 Allegro PCB Editor release, lines and text can now be moved…

• 1 min read
PCB , Allegro 16.6 , SPB , PCB Editor , Layout , Grzenia , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—Select the Right Performance for a 802.11ac/Advanced LTE A…

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind…

• less than a min read
wireless , Whiteboard Wednesdays , 802.11x , wireless AFE , analog front end , AFE , LTE

Digital Design

New Training Class: Get Up to Speed Fast When Migrating to Encounter Digital Implementation…

One question we often hear from experienced physical design engineers migrating to…

• 2 min read
P&R , encounter digital implementation system , place and route , Rapid Adoption Kits , RAKs , physical implementation

SoC and IP

IoT Focus: IoT Applications Require a New Architectural Vision

I wrote earlier that the sheer vastness and potential for IoT designs require a different…

• 3 min read
Consumer Electronics , IoT , IP integration , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

Whiteboard Wednesdays

Whiteboard Wednesdays - Formal VIP for 100% Accurate Designs

In this week's Whiteboard Wednesdays video, Tom Hackett discusses formal verification…

• less than a min read
Whiteboard Wednesdays , Formal Analysis , formal verification IP , formal VIP , Formal verification

SoC and IP

How Do You Build a Wi-Fi 802.11ac Programmable Modem?

The Tensilica® group at Cadence has just published a 37-page application note on…

• 1 min read
Wi-Fi 802.11ac transceiver , Tensilica DSPs , WLAN , LTE , programmable modem

System, PCB, & Package Design 

What's Good About Capture’s Design Rule Checks? 16.6 Has Several New Enhancements…

The Allegro Design Entry CIS (OrCAD Capture) 16.6 release provides extensions to…

• 1 min read
Design Rule Checker , Allegro 16.6 , Design Entry CIS , DRC , 16.6 , Capture CIS , SPB , OrCAD

System, PCB, & Package Design 

Have a Complex, Off-Grid Pin Pattern to Number? Cadence Allegro16.6 IC Package Design…

Complex dies with a mixture of digital and analog circuitry means equally complex…

• 4 min read
IC Packaging and SiP Design , IC Packaging , IC packaging SiP Layout , SiP Design , Digital SiP design , IC Packaging and SiP , layout pin numbering , IC packaging documentation , pin numbering , SiP Layout

Verification

The webinar on “Effective system-level coverage” does an effective coverage of the…

If you're anything like I am, you listen to webinars with one ear, occasionally checking…

• 4 min read
system-level coverage , PXP , hardware assisted verification , webinar , Palladium XP , hardware acceleration , EDA webinar , hardware accelerated verification

System, PCB, & Package Design 

Customer Support Recommended – Using Test Points in Allegro Design Entry CIS and…

A test point is a location within an electronic circuit that is used to either monitor…

• 4 min read
Design Entry CIS , OrCAD Capture Marketplace , Capture CIS , PCB Editor , Constraint Manager , PCB design , test point , Allegro PCB Editor , OrCAD PCB Editor , Schematic , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the…

• less than a min read
Whiteboard Wednesdays , IP , M-PCIe , mobile

Verification

Objection Mechanism Synchronization Between SystemVerilog and e Active Verification…

Suppose you have two verification components, each driving its own portion of the…

• 4 min read
AF , UVM-ML , e-SV , debug , objection mechanism , Functional Verification' signal integrity , Incisive Enterprise Simulator (IES)

Analog/Custom Design

Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online…

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose…

• 3 min read
EAD , AMS , Rapid Adoption Kit , ADE XL , Virtuoso Analog Design Environment , Monte Carlo , Layout , Virtuoso , Virtuosity , statistical corners , Virtuoso Layout Suite , IC 6.1.6

SoC and IP

IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT

You know we live in astonishing times when you can start your car by talking into…

• 2 min read
Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

System, PCB, & Package Design 

Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC Packaging…

Exposing metal through solder mask openings is as necessary as it can be frustrating…

• 4 min read
IC Packaging and SiP Design , SiP , IC Packaging , SiP Design , IC package design , package design rules , Wirebond , SiP Layout , wire bond

System, PCB, & Package Design 

What's Good About Allegro Design Workbench Team Collaboration? Find Out in the 16…

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator…

• 1 min read
PCB , Cadence Design Systems , Allegro 16.6 , cadence , 16.6 , Allegro Design Workbench , Team design , SPB , design , PCB design , Grzenia , ADW

Whiteboard Wednesdays

Whiteboard Wednesdays - USB Controller Connectivity

In this week's Whiteboard Wednesdays, Jacek Duda continues his discussion about USB…

• less than a min read
Whiteboard Wednesdays , USB connectivity , HSIC , USB controllers , SSIC
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