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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
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Blog - Post List

Latest blogs

Analog/Custom Design

What's New(-ish) in ADE XL in IC 616 ISR 3?

Development Model for ADE and ViVA Virtuoso Analog Design Environment (ADE) and…

• 1 min read
Analog Design Environment , ADE XL , Custom IC Design , IC 6.1.6

Whiteboard Wednesdays

Whiteboard Wednesdays - How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application…

• less than a min read
server virtualization , virtualization , IP , hosted virtual desktop , mobile workforces , BYOD

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits …

• 6 min read
IMC , low power simulation , uvm , Specman , LPS , x-propagation , RAK , incisive simulation , LSF , Glitches , state retention , drm , SystemC , vMananger , IES-XL

Digital Design

Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

Friends, you would probably agree that sharing knowledge is a practical way to solve…

• 2 min read
EDI , Encounterer Digital Implementation System , Digital Implementation forums , Tempus , EDI system , Cadence Online Support , digital implementation , Digital Implementation , Encounter Digital Implementation , signoff , timing signoff

Verification

Applying Software-Driven Development Techniques to Testbench Development

Over the past couple of years there has been some interest in applying a software…

• 1 min read
AF , Specman , debug , e code , Funcional Verification , unit testing , Incisive Enterprise Simulator (IES)

System, PCB, & Package Design 

OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of…

• 1 min read
SiP , DDR interface , CDNLive , Co-Design , IC package design , OrbitIO

Whiteboard Wednesdays

Whiteboard Wednesdays - Comparing 3D Memory Solutions and Their Market Applicati…

In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series…

• less than a min read
Whiteboard Wednesdays , 2D Memory , 3D memory , memory wall , SoC design

Analog/Custom Design

Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic…

• 2 min read
ADE GXL , ADE XL , mismatch variation , Virtuoso Analog Design Environment , Monte Carlo , mismatch contribution analysis

Whiteboard Wednesdays

Whiteboard Wednesdays - Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays, Jacek Duda provides an informative overview…

• less than a min read
USB performance specs , Whiteboard Wednesdays , IP , USB 3.X , USB controllers , USB 2.0

System, PCB, & Package Design 

Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2…

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of…

• 2 min read
single and multi-fabric design , full wave 3D field solver , Power Integrity , IC package design , 3DEM , Signal Integrity

System, PCB, & Package Design 

Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging…

To maximize yield and achieve optimum quality of your final, manufactured IC package…

• 4 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging and SiP , IC package design , IC Packaging & SiP design , IC packaging documentation , substrate , SiP Layout

Whiteboard Wednesdays

Whiteboard Wednesdays—The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of…

• less than a min read
LPDDR4 , LPDDR , wide i/o , USB , UFS , eMMC , DRAM , AMBA 5 , OCP , Wide I/O2 , CSI-3 , DDR , Soundwire , PCIe and SSIC. , AMBA 4 , eMMC5 , LPDDR3

System, PCB, & Package Design 

What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!

While there are several videos available for Allegro Design Entry HDL (DEHDL) in…

• 1 min read
PCB , Allegro Design Entry , Allegro 16.6 , PCB design videos , electrical constraints , flat schematics , hierarchical schematics , Allegro 16.5 , SPB , Design Entry HDL , Design Entry , ConceptHDL

Analog/Custom Design

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power…

• 2 min read
Analog Design Environment , ADE GXL , ADE XL , Virtuoso , Custom IC Design , Design Migration

System, PCB, & Package Design 

What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!

There are two new use models for PCB designers using Allegro Design Workbench (ADW…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.6 , Allegro Design Workbench , PCB Editor , design data management , design , PCB design , Allegro PCB Editor , ADW

Whiteboard Wednesdays

Whiteboard Wednesdays - Why Cadence Verification IP (VIP) is a Smart Choice for …

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , SoC design , verifying SoCs

Verification

Cadence Announces Verification IP for MIPI SoundWire and C-PHY

Anyone who has been involved in designing mobile devices in recent years is familiar…

• less than a min read
Verification IP , MIPI Alliance , cadence , audio , PureSpec , Slimbus , VIP , MIPI , CSI , M-PCIe , Denali , C-PHY , Soundwire , M-PHY

Whiteboard Wednesdays

Whiteboard Wednesdays - New MIPI Interfaces: Winners or Losers?

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a…

• less than a min read
Whiteboard Wednesdays , M-PCIe , MIPI protocols , USB , mobile interfaces , mobile

Verification

The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures…

• 4 min read
ARM ecosystem , System Design and Verification , electronics design , Internet of Things , ARM , embedded systems
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